myinst r0,0x14000

Hello, I'm trying to implement an instruction "myinst" that accesses dependent memory locations (similar to pointer chasing) using the TimingCPU model (initiateAcc() and completeAcc()). For example: myinst r0,0x14000 The above line will first read 8 bytes from address 0x14000, which is say 0xFF000. It will then read 8 bytes from address 0xFF000 (or "qword ptr [0x14000]") into register r0. This requires issuing another initiateMemRead() call within the insturction's completeAcc() function. However, I haven't found another example instruction that does this. I wonder whether this is currently supported by TimingCPU and what is the correct way to approach this? Best, Leonard

On 9/25/2023 4:59 PM, Leonard Peterson via gem5-users wrote: > Hello, > > I'm trying to implement an instruction "myinst" that accesses dependent memory locations (similar to > pointer chasing) using the TimingCPU model (initiateAcc() and completeAcc()). For example: > >              myinst r0,0x14000 > > The above line will first read 8 bytes from address 0x14000, which is say 0xFF000. It will then read > 8 bytes from address 0xFF000 (or "qword ptr [0x14000]") into register r0. This requires issuing > another initiateMemRead() call within the insturction's completeAcc() function. However, I haven't > found another example instruction that does this. > > I wonder whether this is currently supported by TimingCPU and what is the correct way to approach this? Intel machines are example of ones that have complex addressing modes. The way gem5 handles this is for the instruction, called a macro instruction, to be broken into two or more micro instructions for execution. This is done in the decoding process. It is typical in the out-of-order cpu, but could apply to other, I think. Hope this helps ... EM