Hi,
You should establish a link between your cache and the ISA. It shouldn't be hard to hack things around.
A cleaner solution would involve using probe points. You could use a probe listener per ISA object. For every alocation update on the l2 cache, the listeners will be awakened and the sysreg value updated accordingly.
Hope this helps
Giacomo
From: tyhtyh--- via gem5-users gem5-users@gem5.org
Sent: 06 March 2024 12:57
To: gem5-users@gem5.org gem5-users@gem5.org
Cc: tyhtyh@mail.ustc.edu.cn tyhtyh@mail.ustc.edu.cn
Subject: [gem5-users] Transfer cache information to misc register in arm
I am a beginner who has just started to learn Gem5. Recently, I attempted to use the msr instruction to read out the currently allocated entries in L2cache (variable "int allocated" in gem5 stable \ src \ mem \ cache \ queue.hh). I have added a new system register for this purpose (by modifying gem5 stable \ src \ arch \ arm \ regs \ misc.hh and misc.cc), and the mrs instruction can correctly read the value of this register. But what confuses me is how to pass this variable to the MiscRegLUTEntry, or in other words, there is an array called RegVal miscRegs [NUM-MISCREGS] in "gem 5 stable \ src \ arch \ arm \ isa. hh" (which I think is used to store different misc register values). What should I do to pass the allocated variable in src \ mem \ cache \ queue.hh to miscRegs [NUM-MISCREGS] in src \ arch \ arm \ isa. hh?Thank you very much for your help！
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hi,
You should establish a link between your cache and the ISA. It shouldn't be hard to hack things around.
A cleaner solution would involve using probe points. You could use a probe listener per ISA object. For every alocation update on the l2 cache, the listeners will be awakened and the sysreg value updated accordingly.
Hope this helps
Giacomo
________________________________
From: tyhtyh--- via gem5-users <gem5-users@gem5.org>
Sent: 06 March 2024 12:57
To: gem5-users@gem5.org <gem5-users@gem5.org>
Cc: tyhtyh@mail.ustc.edu.cn <tyhtyh@mail.ustc.edu.cn>
Subject: [gem5-users] Transfer cache information to misc register in arm
I am a beginner who has just started to learn Gem5. Recently, I attempted to use the msr instruction to read out the currently allocated entries in L2cache (variable "int allocated" in gem5 stable \ src \ mem \ cache \ queue.hh). I have added a new system register for this purpose (by modifying gem5 stable \ src \ arch \ arm \ regs \ misc.hh and misc.cc), and the mrs instruction can correctly read the value of this register. But what confuses me is how to pass this variable to the MiscRegLUTEntry, or in other words, there is an array called RegVal miscRegs [NUM-MISCREGS] in "gem 5 stable \ src \ arch \ arm \ isa. hh" (which I think is used to store different misc register values). What should I do to pass the allocated variable in src \ mem \ cache \ queue.hh to miscRegs [NUM-MISCREGS] in src \ arch \ arm \ isa. hh?Thank you very much for your help！
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
