Empathy List Archives

SD

Sharma, Deepika

Wed, Dec 2, 2020 7:44 PM

I want to calculate the prefetch accuracy for stride prefetcher. I saw that there are two variables usefulPrefetches and issuedPrefetches in Base Pefetcher. These are used in Queued Prefetcher class to calculate prefetch accuracy. I tried using them for stride prefetcher as well. But the value of usefulPrefetches is always 0. Is this a bug or am I understanding something wrong?

Best Regards,
Deepika

I want to calculate the prefetch accuracy for stride prefetcher. I saw that there are two variables usefulPrefetches and issuedPrefetches in Base Pefetcher. These are used in Queued Prefetcher class to calculate prefetch accuracy. I tried using them for stride prefetcher as well. But the value of usefulPrefetches is always 0. Is this a bug or am I understanding something wrong? Best Regards, Deepika

DC

Daniel Carvalho

Thu, Dec 3, 2020 11:27 AM

Hello, Deepika,

Prefetches are currently only considered useful when they are not late. To add late prefetches to the useful ones you will have to modify serviceMSHRTargets(), so that in the case MSHR::Target::FromCPU the prefetcher is notified when the MSHR of a blk->wasPrefetched() is serviced.
By default hits are not notified to the prefetcher; therefore, usefulPrefetches is not updated. To update the number of useful prefetches you have to set prefetch_on_access=True in the cache. This does not seem correct, so I've uploaded a proposed fix for review: https://gem5-review.googlesource.com/c/public/gem5/+/38177/1.

Minor note: if you are using the develop branch, or have applied commit https://gem5-review.googlesource.com/c/public/gem5/+/35699 locally, it must be fixed with the following patch: https://gem5-review.googlesource.com/c/public/gem5/+/38176
Regards,Daniel #yiv9065000498 P {margin-top:0;margin-bottom:0;}I want to calculate the prefetch accuracy for stride prefetcher. I saw that there are two variables usefulPrefetches and issuedPrefetches in Base Pefetcher. These are used in Queued Prefetcher class to calculate prefetch accuracy. I tried using them for stride prefetcher as well. But the value of usefulPrefetches is always 0. Is this a bug or am I understanding something wrong?
Best Regards,Deepika

Hello, Deepika, Prefetches are currently only considered useful when they are not late. To add late prefetches to the useful ones you will have to modify serviceMSHRTargets(), so that in the case MSHR::Target::FromCPU the prefetcher is notified when the MSHR of a blk->wasPrefetched() is serviced. By default hits are not notified to the prefetcher; therefore, usefulPrefetches is not updated. To update the number of useful prefetches you have to set prefetch_on_access=True in the cache. This does not seem correct, so I've uploaded a proposed fix for review: https://gem5-review.googlesource.com/c/public/gem5/+/38177/1. Minor note: if you are using the develop branch, or have applied commit https://gem5-review.googlesource.com/c/public/gem5/+/35699 locally, it must be fixed with the following patch: https://gem5-review.googlesource.com/c/public/gem5/+/38176 Regards,Daniel #yiv9065000498 P {margin-top:0;margin-bottom:0;}I want to calculate the prefetch accuracy for stride prefetcher. I saw that there are two variables usefulPrefetches and issuedPrefetches in Base Pefetcher. These are used in Queued Prefetcher class to calculate prefetch accuracy. I tried using them for stride prefetcher as well. But the value of usefulPrefetches is always 0. Is this a bug or am I understanding something wrong? Best Regards,Deepika

DB

David Bose, Christin

Thu, Dec 3, 2020 7:40 PM

Hi,

I was trying to profile some INT registers for measuring value locality. I was reading the value of RegIndex as defined in the reg_class.hh file found in src/cpu. I was under the impression that this gives out the logical index of the architectural register. However, on reading out some values, it seems RegIndex gets values as high as 43. I thought ARM had fewer registers than that.

Please help to clarify this.

[cid:c84350e1-b356-406a-8bb0-296f843591da]

Thanks.

Regards,
Christin

Hi, I was trying to profile some INT registers for measuring value locality. I was reading the value of RegIndex as defined in the reg_class.hh file found in src/cpu. I was under the impression that this gives out the logical index of the architectural register. However, on reading out some values, it seems RegIndex gets values as high as 43. I thought ARM had fewer registers than that. Please help to clarify this. [cid:c84350e1-b356-406a-8bb0-296f843591da] Thanks. Regards, Christin

GT

Giacomo Travaglini

Mon, Dec 7, 2020 10:00 AM

Hi,

I suggest you to have a look at src/arch/arm/intregs.hh to see how the indexes are defined.
You will notice how both NUM_ARCH_INTREGS and NUM_INT_REGS are defined. The first refers to the architectural limit, the second accounts for register banking (in AArch32) and it's bigger than NUM_ARCH_INTREGS

Are you checking the value when the execution state is in AArch32?

Kind Regards

Giacomo

-----Original Message-----
From: David Bose, Christin via gem5-users <gem5-users(a)gem5.org>
Sent: 03 December 2020 19:40
To: gem5-users(a)gem5.org
Cc: David Bose, Christin <chris241(a)purdue.edu>
Subject: [gem5-users] Number of architectural registers for ARM ISA

Hi,

I was trying to profile some INT registers for measuring value locality. I was
reading the value of RegIndex as defined in the reg_class.hh file found in
src/cpu. I was under the impression that this gives out the logical index of the
architectural register. However, on reading out some values, it seems RegIndex
gets values as high as 43. I thought ARM had fewer registers than that.

Please help to clarify this.

Thanks.

Regards,
Christin

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Hi, I suggest you to have a look at src/arch/arm/intregs.hh to see how the indexes are defined. You will notice how both NUM_ARCH_INTREGS and NUM_INT_REGS are defined. The first refers to the architectural limit, the second accounts for register banking (in AArch32) and it's bigger than NUM_ARCH_INTREGS Are you checking the value when the execution state is in AArch32? Kind Regards Giacomo > -----Original Message----- > From: David Bose, Christin via gem5-users <gem5-users(a)gem5.org> > Sent: 03 December 2020 19:40 > To: gem5-users(a)gem5.org > Cc: David Bose, Christin <chris241(a)purdue.edu> > Subject: [gem5-users] Number of architectural registers for ARM ISA > > Hi, > > I was trying to profile some INT registers for measuring value locality. I was > reading the value of RegIndex as defined in the reg_class.hh file found in > src/cpu. I was under the impression that this gives out the logical index of the > architectural register. However, on reading out some values, it seems RegIndex > gets values as high as 43. I thought ARM had fewer registers than that. > > Please help to clarify this. > > > > > Thanks. > > Regards, > Christin > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

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Prefetch Accuracy