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[L] Change in gem5/gem5[develop]: tests: Update tests to use ALL/gem5.opt compilation

BB
Bobby Bruce (Gerrit)
Thu, Sep 22, 2022 6:19 PM

Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/63374?usp=email )

Change subject: tests: Update tests to use ALL/gem5.opt compilation
......................................................................

tests: Update tests to use ALL/gem5.opt compilation

Where possible the gem5 tests have been updated to use the
build/ALL/gem5.opt compilation.

If a quick test requied a specific a ISA/protocol compilation they
were moved to the long/nightly set. This means all the quick/kokoro
tests are run with the build/ALL/gem5.opt compilation.

The learning_gem5 tests have been updated to use ALL/gem5.opt.

The equivilant examples on the website have been updated via:
https://gem5-review.googlesource.com/c/public/gem5-website/+/63336

Change-Id: I533689ad6848233867bdba9e9a43bb5840ed65c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63374
Tested-by: kokoro noreply+kokoro@google.com
Reviewed-by: Giacomo Travaglini giacomo.travaglini@arm.com
Maintainer: Bobby Bruce bbruce@ucdavis.edu

M configs/example/gem5_library/arm-ubuntu-boot-exit.py
A configs/learning_gem5/part1/simple-arm.py
A configs/learning_gem5/part1/simple-riscv.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/simple_ruby.py
M tests/gem5/asmtest/tests.py
M tests/gem5/configs/arm_generic.py
A tests/gem5/configs/base_caches.py
M tests/gem5/configs/base_config.py
M tests/gem5/configs/realview-minor.py
M tests/gem5/configs/realview-simple-atomic-checkpoint.py
M tests/gem5/configs/realview-simple-atomic-dual.py
M tests/gem5/configs/realview-simple-atomic.py
M tests/gem5/configs/realview-simple-timing-dual-ruby.py
M tests/gem5/configs/realview-simple-timing-dual.py
M tests/gem5/configs/realview-simple-timing-ruby.py
M tests/gem5/configs/realview-simple-timing.py
M tests/gem5/configs/realview-switcheroo-atomic.py
M tests/gem5/configs/realview-switcheroo-full.py
M tests/gem5/configs/realview-switcheroo-noncaching-timing.py
M tests/gem5/configs/realview-switcheroo-o3.py
M tests/gem5/configs/realview-switcheroo-timing.py
M tests/gem5/configs/realview64-minor-dual.py
M tests/gem5/configs/realview64-minor.py
M tests/gem5/configs/realview64-o3-dual-ruby.py
M tests/gem5/configs/realview64-simple-atomic-checkpoint.py
M tests/gem5/configs/realview64-simple-atomic-dual.py
M tests/gem5/configs/realview64-simple-atomic.py
M tests/gem5/configs/realview64-simple-timing-dual-ruby.py
M tests/gem5/configs/realview64-simple-timing-dual.py
M tests/gem5/configs/realview64-simple-timing-ruby.py
M tests/gem5/configs/realview64-simple-timing.py
M tests/gem5/configs/realview64-switcheroo-atomic.py
M tests/gem5/configs/realview64-switcheroo-full.py
M tests/gem5/configs/realview64-switcheroo-o3.py
M tests/gem5/configs/realview64-switcheroo-timing.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/switcheroo.py
M tests/gem5/cpu_tests/run.py
M tests/gem5/cpu_tests/test.py
M tests/gem5/dram-lowp/test_dram_lowp.py
M tests/gem5/fs/linux/arm/test.py
M tests/gem5/gem5-resources/test_download_resources.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
M tests/gem5/gpu/test_gpu_ruby_random.py
M tests/gem5/insttest_se/test.py
M tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
M tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
M tests/gem5/learning_gem5/part1_test.py
M tests/gem5/learning_gem5/part2_test.py
M tests/gem5/learning_gem5/part3_test.py
M tests/gem5/m5_util/test_exit.py
M tests/gem5/m5threads_test_atomic/atomic_system.py
M tests/gem5/memory/test.py
M tests/gem5/multi_isa/test_multi_isa.py
M tests/gem5/parsec-benchmarks/test_parsec.py
M tests/gem5/riscv-boot-tests/test_linux_boot.py
M tests/gem5/se_mode/hello_se/test_hello_se.py
M tests/gem5/se_mode/hello_se/test_se_multicore.py
M tests/gem5/stats/test_hdf5.py
M tests/gem5/stdlib/test_base_cpu_processor.py
M tests/gem5/stdlib/test_requires.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
M tests/gem5/x86-boot-tests/test_linux_boot.py
M tests/pyunit/test_run.py
70 files changed, 480 insertions(+), 225 deletions(-)

Approvals:
Bobby Bruce: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass

diff --git a/configs/example/gem5_library/arm-ubuntu-boot-exit.py
b/configs/example/gem5_library/arm-ubuntu-boot-exit.py
index 69984a9..201fb23 100644
--- a/configs/example/gem5_library/arm-ubuntu-boot-exit.py
+++ b/configs/example/gem5_library/arm-ubuntu-boot-exit.py
@@ -76,7 +76,7 @@

Here we setup the processor. We use a simple TIMING processor. The config

script was also tested with ATOMIC processor.

-processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2)
+processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2,
isa=ISA.ARM)

The ArmBoard requires a release to be specified. This adds all the

extensions or features to the system. We are setting this to Armv8

diff --git a/configs/learning_gem5/part1/simple-arm.py
b/configs/learning_gem5/part1/simple-arm.py
new file mode 100644
index 0000000..62f7645
--- /dev/null
+++ b/configs/learning_gem5/part1/simple-arm.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This is the ARM equivalent to simple.py (which is designed to run using
the
+X86 ISA). More detailed documentation can be found in simple.py.
+"""
+
+import m5
+from m5.objects import *
+
+system = System()
+
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = "1GHz"
+system.clk_domain.voltage_domain = VoltageDomain()
+
+system.mem_mode = "timing"
+system.mem_ranges = [AddrRange("512MB")]
+system.cpu = ArmTimingSimpleCPU()
+
+system.membus = SystemXBar()
+
+system.cpu.icache_port = system.membus.cpu_side_ports
+system.cpu.dcache_port = system.membus.cpu_side_ports
+
+system.cpu.createInterruptController()
+
+system.mem_ctrl = MemCtrl()
+system.mem_ctrl.dram = DDR3_1600_8x8()
+system.mem_ctrl.dram.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.mem_side_ports
+
+system.system_port = system.membus.cpu_side_ports
+
+thispath = os.path.dirname(os.path.realpath(file))
+binary = os.path.join(

  • thispath,
  • "../../../",
  • "tests/test-progs/hello/bin/arm/linux/hello",
    +)

+system.workload = SEWorkload.init_compatible(binary)
+
+process = Process()
+process.cmd = [binary]
+system.cpu.workload = process
+system.cpu.createThreads()
+
+root = Root(full_system=False, system=system)
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print("Exiting @ tick %i because %s" % (m5.curTick(),
exit_event.getCause()))
diff --git a/configs/learning_gem5/part1/simple-riscv.py
b/configs/learning_gem5/part1/simple-riscv.py
new file mode 100644
index 0000000..f05ca4a
--- /dev/null
+++ b/configs/learning_gem5/part1/simple-riscv.py
@@ -0,0 +1,78 @@
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This is the RISCV equivalent to simple.py (which is designed to run
using the
+X86 ISA). More detailed documentation can be found in simple.py.
+"""
+
+import m5
+from m5.objects import *
+
+system = System()
+
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = "1GHz"
+system.clk_domain.voltage_domain = VoltageDomain()
+
+system.mem_mode = "timing"
+system.mem_ranges = [AddrRange("512MB")]
+system.cpu = RiscvTimingSimpleCPU()
+
+system.membus = SystemXBar()
+
+system.cpu.icache_port = system.membus.cpu_side_ports
+system.cpu.dcache_port = system.membus.cpu_side_ports
+
+system.cpu.createInterruptController()
+
+system.mem_ctrl = MemCtrl()
+system.mem_ctrl.dram = DDR3_1600_8x8()
+system.mem_ctrl.dram.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.mem_side_ports
+
+system.system_port = system.membus.cpu_side_ports
+
+thispath = os.path.dirname(os.path.realpath(file))
+binary = os.path.join(

  • thispath,
  • "../../../",
  • "tests/test-progs/hello/bin/riscv/linux/hello",
    +)

+system.workload = SEWorkload.init_compatible(binary)
+
+process = Process()
+process.cmd = [binary]
+system.cpu.workload = process
+system.cpu.createThreads()
+
+root = Root(full_system=False, system=system)
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print("Exiting @ tick %i because %s" % (m5.curTick(),
exit_event.getCause()))
diff --git a/configs/learning_gem5/part1/simple.py
b/configs/learning_gem5/part1/simple.py
index f3570ed..e36cd78 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -1,4 +1,3 @@
-# -- coding: utf-8 --

Copyright (c) 2015 Jason Power

All rights reserved.

@@ -33,6 +32,10 @@
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
also needs to be updated. For now, email Jason
power.jg@gmail.com

+This script uses the X86 ISA. simple-arm.py and simple-riscv.py may be
+referenced as examples of scripts which utilize the ARM and RISC-V ISAs
+respectively.
+
"""

import the m5 (gem5) library created when gem5 is built

@@ -40,8 +43,6 @@

import all of the SimObjects

from m5.objects import *
-from gem5.isas import ISA
-from gem5.runtime import get_runtime_isa

create the system we are going to simulate

system = System()
@@ -56,7 +57,9 @@
system.mem_ranges = [AddrRange("512MB")]  # Create an address range

Create a simple CPU

-system.cpu = TimingSimpleCPU()
+# You can use ISA-specific CPU models for different workloads:
+# RiscvTimingSimpleCPU, ArmTimingSimpleCPU.
+system.cpu = X86TimingSimpleCPU()

Create a memory bus, a system crossbar, in this case

system.membus = SystemXBar()
@@ -68,12 +71,12 @@

create the interrupt controller for the CPU and connect to the membus

system.cpu.createInterruptController()

-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if get_runtime_isa() == ISA.X86:

  • system.cpu.interrupts[0].pio = system.membus.mem_side_ports
  • system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
  • system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
    +# For X86 only we make sure the interrupts care connect to memory.
    +# Note: these are directly connected to the memory bus and are not cached.
    +# For other ISA you should remove the following three lines.
    +system.cpu.interrupts[0].pio = system.membus.mem_side_ports
    +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
    +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports

Create a DDR3 memory controller and connect it to the membus

system.mem_ctrl = MemCtrl()
@@ -84,18 +87,14 @@

Connect the system up to the membus

system.system_port = system.membus.cpu_side_ports

-# get ISA for the binary to run.
-isa = get_runtime_isa()

-# Default to running 'hello', use the compiled ISA to find the binary
-# grab the specific path to the binary
+# Here we set the X86 "hello world" binary. With other ISAs you must
specify
+# workloads compiled to those ISAs. Other "hello world" binaries for other
ISAs
+# can be found in "tests/test-progs/hello".
thispath = os.path.dirname(os.path.realpath(file))
binary = os.path.join(
thispath,
"../../../",

  • "tests/test-progs/hello/bin/",
  • isa.name.lower(),
  • "linux/hello",
  • "tests/test-progs/hello/bin/x86/linux/hello",
    )

system.workload = SEWorkload.init_compatible(binary)
diff --git a/configs/learning_gem5/part1/two_level.py
b/configs/learning_gem5/part1/two_level.py
index 905e286..8aa7dd7 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -43,7 +43,6 @@

import all of the SimObjects

from m5.objects import *
-from gem5.isas import ISA
from gem5.runtime import get_runtime_isa

Add the common scripts to our path

@@ -55,18 +54,13 @@

import the SimpleOpts module

from common import SimpleOpts

-# get ISA for the default binary to run. This is mostly for simple testing
-isa = get_runtime_isa()

Default to running 'hello', use the compiled ISA to find the binary

grab the specific path to the binary

thispath = os.path.dirname(os.path.realpath(file))
default_binary = os.path.join(
thispath,
"../../../",

  • "tests/test-progs/hello/bin/",
  • isa.name.lower(),
  • "linux/hello",
  • "tests/test-progs/hello/bin/x86/linux/hello",
    )

Binary to execute

@@ -88,7 +82,7 @@
system.mem_ranges = [AddrRange("512MB")]  # Create an address range

Create a simple CPU

-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()

Create an L1 instruction and data cache

system.cpu.icache = L1ICache(args)
@@ -117,13 +111,9 @@

create the interrupt controller for the CPU

system.cpu.createInterruptController()

-# For x86 only, make sure the interrupts are connected to the memory
-# Note: these are directly connected to the memory bus and are not cached
-if isa == ISA.X86:

  • system.cpu.interrupts[0].pio = system.membus.mem_side_ports
  • system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
  • system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
    +system.cpu.interrupts[0].pio = system.membus.mem_side_ports
    +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
    +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports

Connect the system up to the membus

system.system_port = system.membus.cpu_side_ports
diff --git a/configs/learning_gem5/part2/simple_cache.py
b/configs/learning_gem5/part2/simple_cache.py
index 0a27979..4228956 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -50,7 +50,7 @@
system.mem_ranges = [AddrRange("512MB")]  # Create an address range

Create a simple CPU

-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()

Create a memory bus, a coherent crossbar, in this case

system.membus = SystemXBar()
diff --git a/configs/learning_gem5/part2/simple_memobj.py
b/configs/learning_gem5/part2/simple_memobj.py
index ff4a2c9..20f4362 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -50,7 +50,7 @@
system.mem_ranges = [AddrRange("512MB")]  # Create an address range

Create a simple CPU

-system.cpu = TimingSimpleCPU()
+system.cpu = X86TimingSimpleCPU()

Create the simple memory object

system.memobj = SimpleMemobj()
diff --git a/configs/learning_gem5/part3/msi_caches.py
b/configs/learning_gem5/part3/msi_caches.py
index 8567571..13b2a11 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -39,8 +39,6 @@

from m5.defines import buildEnv
from m5.util import fatal, panic
-from gem5.isas import ISA
-from gem5.runtime import get_runtime_isa

from m5.objects import *

@@ -148,10 +146,10 @@
1. The O3 model must keep the LSQ coherent with the caches
2. The x86 mwait instruction is built on top of coherence
3. The local exclusive monitor in ARM systems
+

  •    As this is an X86 simulation we return True.
        """
    
  •    if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86,  
    

ISA.ARM):

  •        return True
    
  •    return False
    
  •    return True
    
    def connectQueues(self, ruby_system):
        """Connect all of the queues for this controller."""
    

diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py
b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index 2374ca0..8c25a9b 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -41,8 +41,6 @@

from m5.defines import buildEnv
from m5.util import fatal, panic
-from gem5.isas import ISA
-from gem5.runtime import get_runtime_isa

from m5.objects import *

@@ -146,10 +144,10 @@
1. The O3 model must keep the LSQ coherent with the caches
2. The x86 mwait instruction is built on top of coherence
3. The local exclusive monitor in ARM systems
+

  •    As this is an X86 simulation we return True.
        """
    
  •    if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86,  
    

ISA.ARM):

  •        return True
    
  •    return False
    
  •    return True
    
    def connectQueues(self, ruby_system):
        """Connect all of the queues for this controller."""
    

diff --git a/configs/learning_gem5/part3/simple_ruby.py
b/configs/learning_gem5/part3/simple_ruby.py
index 7637935..b62a719 100644
--- a/configs/learning_gem5/part3/simple_ruby.py
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -42,7 +42,6 @@

import all of the SimObjects

from m5.objects import *
-from gem5.runtime import get_runtime_isa

Needed for running C++ threads

m5.util.addToPath("../../")
@@ -65,7 +64,7 @@
system.mem_ranges = [AddrRange("512MB")]  # Create an address range

Create a pair of simple CPUs

-system.cpu = [TimingSimpleCPU() for i in range(2)]
+system.cpu = [X86TimingSimpleCPU() for i in range(2)]

Create a DDR3 memory controller and connect it to the membus

system.mem_ctrl = MemCtrl()
@@ -80,18 +79,13 @@
system.caches = MyCacheSystem()
system.caches.setup(system, system.cpu, [system.mem_ctrl])

-# get ISA for the binary to run.
-isa = get_runtime_isa()

Run application and use the compiled ISA to find the binary

grab the specific path to the binary

thispath = os.path.dirname(os.path.realpath(file))
binary = os.path.join(
thispath,
"../../../",

  • "tests/test-progs/threads/bin/",
  • isa.name.lower(),
  • "linux/threads",
  • "tests/test-progs/threads/bin/x86/linux/threads",
    )

Create a process for a simple "multi-threaded" application

diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index cdaf556..b2a5992 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -192,6 +192,6 @@
"--resource-directory",
resource_path,
],

  •        valid_isas=(constants.riscv_tag,),
    
  •        valid_isas=(constants.all_compiled_tag,),
            valid_hosts=constants.supported_hosts,
        )
    

diff --git a/tests/gem5/configs/arm_generic.py
b/tests/gem5/configs/arm_generic.py
index 8408123..252ac6c 100644
--- a/tests/gem5/configs/arm_generic.py
+++ b/tests/gem5/configs/arm_generic.py
@@ -40,7 +40,7 @@

m5.util.addToPath("../configs/")
from common import FSConfig
-from common.Caches import *
+from base_caches import *
from base_config import *
from common.cores.arm.O3_ARM_v7a import *
from common.Benchmarks import SysConfig
diff --git a/tests/gem5/configs/base_caches.py
b/tests/gem5/configs/base_caches.py
new file mode 100644
index 0000000..3b5f558
--- /dev/null
+++ b/tests/gem5/configs/base_caches.py
@@ -0,0 +1,85 @@
+# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2020 Barkhausen Institut
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects import *
+
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+
+class L1Cache(Cache):

  • assoc = 2
  • tag_latency = 2
  • data_latency = 2
  • response_latency = 2
  • mshrs = 4
  • tgts_per_mshr = 20

+class L1_ICache(L1Cache):

  • is_read_only = True
  • Writeback clean lines as well

  • writeback_clean = True

+class L1_DCache(L1Cache):

  • pass

+class L2Cache(Cache):

  • assoc = 8
  • tag_latency = 20
  • data_latency = 20
  • response_latency = 20
  • mshrs = 20
  • tgts_per_mshr = 12
  • write_buffers = 8

+class IOCache(Cache):

  • assoc = 8
  • tag_latency = 50
  • data_latency = 50
  • response_latency = 50
  • mshrs = 20
  • size = "1kB"
  • tgts_per_mshr = 12
    diff --git a/tests/gem5/configs/base_config.py
    b/tests/gem5/configs/base_config.py
    index e190df1..22987d5 100644
    --- a/tests/gem5/configs/base_config.py
    +++ b/tests/gem5/configs/base_config.py
    @@ -40,7 +40,7 @@
    from m5.proxy import *
    from common import FSConfig
    from common import Options
    -from common.Caches import *
    +from base_caches import *
    from ruby import Ruby

_have_kvm_support = "BaseKvmCPU" in globals()
diff --git a/tests/gem5/configs/realview-minor.py
b/tests/gem5/configs/realview-minor.py
index cb85516..a635162 100644
--- a/tests/gem5/configs/realview-minor.py
+++ b/tests/gem5/configs/realview-minor.py
@@ -41,5 +41,5 @@
machine_type="VExpress_GEM5_V1",
mem_mode="timing",
mem_class=DDR3_1600_8x8,

  • cpu_class=MinorCPU,
  • cpu_class=ArmMinorCPU,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-atomic-checkpoint.py
    b/tests/gem5/configs/realview-simple-atomic-checkpoint.py
    index 9dbb48e..a60fd96 100644
    --- a/tests/gem5/configs/realview-simple-atomic-checkpoint.py
    +++ b/tests/gem5/configs/realview-simple-atomic-checkpoint.py
    @@ -44,7 +44,7 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="atomic",
    mem_class=SimpleMemory,
  • cpu_class=AtomicSimpleCPU,
  • cpu_class=ArmAtomicSimpleCPU,
    ).create_root()

run_test = functools.partial(checkpoint.run_test, interval=0.2)
diff --git a/tests/gem5/configs/realview-simple-atomic-dual.py
b/tests/gem5/configs/realview-simple-atomic-dual.py
index 7aded86..c02f872 100644
--- a/tests/gem5/configs/realview-simple-atomic-dual.py
+++ b/tests/gem5/configs/realview-simple-atomic-dual.py
@@ -41,6 +41,6 @@
machine_type="VExpress_GEM5_V1",
mem_mode="atomic",
mem_class=SimpleMemory,

  • cpu_class=AtomicSimpleCPU,
  • cpu_class=ArmAtomicSimpleCPU,
    num_cpus=2,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-atomic.py
    b/tests/gem5/configs/realview-simple-atomic.py
    index cb286dd..9c782ad 100644
    --- a/tests/gem5/configs/realview-simple-atomic.py
    +++ b/tests/gem5/configs/realview-simple-atomic.py
    @@ -41,5 +41,5 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="atomic",
    mem_class=SimpleMemory,
  • cpu_class=AtomicSimpleCPU,
  • cpu_class=ArmAtomicSimpleCPU,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-timing-dual-ruby.py
    b/tests/gem5/configs/realview-simple-timing-dual-ruby.py
    index cf4da18..741eded 100644
    --- a/tests/gem5/configs/realview-simple-timing-dual-ruby.py
    +++ b/tests/gem5/configs/realview-simple-timing-dual-ruby.py
    @@ -41,7 +41,7 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    num_cpus=2,
    use_ruby=True,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-timing-dual.py
    b/tests/gem5/configs/realview-simple-timing-dual.py
    index b6c84e9..aaea9de 100644
    --- a/tests/gem5/configs/realview-simple-timing-dual.py
    +++ b/tests/gem5/configs/realview-simple-timing-dual.py
    @@ -41,6 +41,6 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    num_cpus=2,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-timing-ruby.py
    b/tests/gem5/configs/realview-simple-timing-ruby.py
    index 4f7f73e..fcca943 100644
    --- a/tests/gem5/configs/realview-simple-timing-ruby.py
    +++ b/tests/gem5/configs/realview-simple-timing-ruby.py
    @@ -41,6 +41,6 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    use_ruby=True,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-simple-timing.py
    b/tests/gem5/configs/realview-simple-timing.py
    index 38cab57..2afbdd0 100644
    --- a/tests/gem5/configs/realview-simple-timing.py
    +++ b/tests/gem5/configs/realview-simple-timing.py
    @@ -41,5 +41,5 @@
    machine_type="VExpress_GEM5_V1",
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    ).create_root()
    diff --git a/tests/gem5/configs/realview-switcheroo-atomic.py
    b/tests/gem5/configs/realview-switcheroo-atomic.py
    index 1f64660..d2f2100 100644
    --- a/tests/gem5/configs/realview-switcheroo-atomic.py
    +++ b/tests/gem5/configs/realview-switcheroo-atomic.py
    @@ -38,7 +38,8 @@
    import switcheroo

root = LinuxArmFSSwitcheroo(

  • mem_class=SimpleMemory, cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
  • mem_class=SimpleMemory,
  • cpu_classes=(ArmAtomicSimpleCPU, ArmAtomicSimpleCPU),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview-switcheroo-full.py
b/tests/gem5/configs/realview-switcheroo-full.py
index f3a7d03..6ed99a3 100644
--- a/tests/gem5/configs/realview-switcheroo-full.py
+++ b/tests/gem5/configs/realview-switcheroo-full.py
@@ -41,7 +41,12 @@
machine_type="VExpress_GEM5_V1",
aarch64_kernel=False,
mem_class=DDR3_1600_8x8,

  • cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU),
  • cpu_classes=(
  •    ArmAtomicSimpleCPU,
    
  •    ArmTimingSimpleCPU,
    
  •    ArmMinorCPU,
    
  •    ArmO3CPU,
    
  • ),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview-switcheroo-noncaching-timing.py
b/tests/gem5/configs/realview-switcheroo-noncaching-timing.py
index 9fbac61..cc77f44 100644
--- a/tests/gem5/configs/realview-switcheroo-noncaching-timing.py
+++ b/tests/gem5/configs/realview-switcheroo-noncaching-timing.py
@@ -38,7 +38,7 @@
import switcheroo

root = LinuxArmFSSwitcheroo(

  • cpu_classes=(NonCachingSimpleCPU, TimingSimpleCPU)
  • cpu_classes=(ArmNonCachingSimpleCPU, ArmTimingSimpleCPU)
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview-switcheroo-o3.py
b/tests/gem5/configs/realview-switcheroo-o3.py
index 7eee6eb..fe3298f 100644
--- a/tests/gem5/configs/realview-switcheroo-o3.py
+++ b/tests/gem5/configs/realview-switcheroo-o3.py
@@ -41,7 +41,7 @@
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",
mem_class=DDR3_1600_8x8,

  • cpu_classes=(DerivO3CPU, DerivO3CPU),
  • cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview-switcheroo-timing.py
b/tests/gem5/configs/realview-switcheroo-timing.py
index eff1e80..5157da6 100644
--- a/tests/gem5/configs/realview-switcheroo-timing.py
+++ b/tests/gem5/configs/realview-switcheroo-timing.py
@@ -38,7 +38,8 @@
import switcheroo

root = LinuxArmFSSwitcheroo(

  • mem_class=DDR3_1600_8x8, cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
  • mem_class=DDR3_1600_8x8,
  • cpu_classes=(ArmTimingSimpleCPU, ArmTimingSimpleCPU),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview64-minor-dual.py
b/tests/gem5/configs/realview64-minor-dual.py
index f067170..aed5d83 100644
--- a/tests/gem5/configs/realview64-minor-dual.py
+++ b/tests/gem5/configs/realview64-minor-dual.py
@@ -37,5 +37,8 @@
from arm_generic import *

root = LinuxArmFSSystem(

  • mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=MinorCPU,
    num_cpus=2
  • mem_mode="timing",
  • mem_class=DDR3_1600_8x8,
  • cpu_class=ArmMinorCPU,
  • num_cpus=2,
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-minor.py
    b/tests/gem5/configs/realview64-minor.py
    index d1c6d93..7bad3c5 100644
    --- a/tests/gem5/configs/realview64-minor.py
    +++ b/tests/gem5/configs/realview64-minor.py
    @@ -37,5 +37,5 @@
    from arm_generic import *

root = LinuxArmFSSystemUniprocessor(

  • mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=MinorCPU
  • mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmMinorCPU
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-o3-dual-ruby.py
    b/tests/gem5/configs/realview64-o3-dual-ruby.py
    index 97e0090..a4bffe9 100644
    --- a/tests/gem5/configs/realview64-o3-dual-ruby.py
    +++ b/tests/gem5/configs/realview64-o3-dual-ruby.py
    @@ -39,7 +39,7 @@
    root = LinuxArmFSSystem(
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=O3CPU,
  • cpu_class=ArmO3CPU,
    num_cpus=2,
    enable_dvm=True,
    use_ruby=True,
    diff --git a/tests/gem5/configs/realview64-simple-atomic-checkpoint.py
    b/tests/gem5/configs/realview64-simple-atomic-checkpoint.py
    index c595037..fa73a0e 100644
    --- a/tests/gem5/configs/realview64-simple-atomic-checkpoint.py
    +++ b/tests/gem5/configs/realview64-simple-atomic-checkpoint.py
    @@ -40,7 +40,7 @@
    import checkpoint

root = LinuxArmFSSystemUniprocessor(

  • mem_mode="atomic", mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU
  • mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU
    ).create_root()

run_test = functools.partial(
diff --git a/tests/gem5/configs/realview64-simple-atomic-dual.py
b/tests/gem5/configs/realview64-simple-atomic-dual.py
index 26ba53a..19cf751 100644
--- a/tests/gem5/configs/realview64-simple-atomic-dual.py
+++ b/tests/gem5/configs/realview64-simple-atomic-dual.py
@@ -39,6 +39,6 @@
root = LinuxArmFSSystem(
mem_mode="atomic",
mem_class=SimpleMemory,

  • cpu_class=AtomicSimpleCPU,
  • cpu_class=ArmAtomicSimpleCPU,
    num_cpus=2,
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-simple-atomic.py
    b/tests/gem5/configs/realview64-simple-atomic.py
    index f9d30a4..299dd7b 100644
    --- a/tests/gem5/configs/realview64-simple-atomic.py
    +++ b/tests/gem5/configs/realview64-simple-atomic.py
    @@ -37,5 +37,5 @@
    from arm_generic import *

root = LinuxArmFSSystemUniprocessor(

  • mem_mode="atomic", mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU
  • mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-simple-timing-dual-ruby.py
    b/tests/gem5/configs/realview64-simple-timing-dual-ruby.py
    index 991ed14..96ad963 100644
    --- a/tests/gem5/configs/realview64-simple-timing-dual-ruby.py
    +++ b/tests/gem5/configs/realview64-simple-timing-dual-ruby.py
    @@ -39,7 +39,7 @@
    root = LinuxArmFSSystem(
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    num_cpus=2,
    use_ruby=True,
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-simple-timing-dual.py
    b/tests/gem5/configs/realview64-simple-timing-dual.py
    index 1e658df..8b62cd3 100644
    --- a/tests/gem5/configs/realview64-simple-timing-dual.py
    +++ b/tests/gem5/configs/realview64-simple-timing-dual.py
    @@ -39,6 +39,6 @@
    root = LinuxArmFSSystem(
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    num_cpus=2,
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-simple-timing-ruby.py
    b/tests/gem5/configs/realview64-simple-timing-ruby.py
    index 8ed0287..f602453 100644
    --- a/tests/gem5/configs/realview64-simple-timing-ruby.py
    +++ b/tests/gem5/configs/realview64-simple-timing-ruby.py
    @@ -39,6 +39,6 @@
    root = LinuxArmFSSystemUniprocessor(
    mem_mode="timing",
    mem_class=DDR3_1600_8x8,
  • cpu_class=TimingSimpleCPU,
  • cpu_class=ArmTimingSimpleCPU,
    use_ruby=True,
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-simple-timing.py
    b/tests/gem5/configs/realview64-simple-timing.py
    index 5c96506..6897f3b 100644
    --- a/tests/gem5/configs/realview64-simple-timing.py
    +++ b/tests/gem5/configs/realview64-simple-timing.py
    @@ -37,5 +37,5 @@
    from arm_generic import *

root = LinuxArmFSSystemUniprocessor(

  • mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=TimingSimpleCPU
  • mem_mode="timing", mem_class=DDR3_1600_8x8,
    cpu_class=ArmTimingSimpleCPU
    ).create_root()
    diff --git a/tests/gem5/configs/realview64-switcheroo-atomic.py
    b/tests/gem5/configs/realview64-switcheroo-atomic.py
    index 12e57ed..c2f67f0 100644
    --- a/tests/gem5/configs/realview64-switcheroo-atomic.py
    +++ b/tests/gem5/configs/realview64-switcheroo-atomic.py
    @@ -38,7 +38,8 @@
    import switcheroo

root = LinuxArmFSSwitcheroo(

  • mem_class=SimpleMemory, cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
  • mem_class=SimpleMemory,
  • cpu_classes=(ArmAtomicSimpleCPU, ArmAtomicSimpleCPU),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview64-switcheroo-full.py
b/tests/gem5/configs/realview64-switcheroo-full.py
index 0685255..abc96f9 100644
--- a/tests/gem5/configs/realview64-switcheroo-full.py
+++ b/tests/gem5/configs/realview64-switcheroo-full.py
@@ -39,7 +39,12 @@

root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_8x8,

  • cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU),
  • cpu_classes=(
  •    ArmAtomicSimpleCPU,
    
  •    ArmTimingSimpleCPU,
    
  •    ArmMinorCPU,
    
  •    ArmDerivO3CPU,
    
  • ),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py
b/tests/gem5/configs/realview64-switcheroo-o3.py
index 833e6a4..ddfc73a 100644
--- a/tests/gem5/configs/realview64-switcheroo-o3.py
+++ b/tests/gem5/configs/realview64-switcheroo-o3.py
@@ -38,7 +38,7 @@
import switcheroo

root = LinuxArmFSSwitcheroo(

  • mem_class=DDR3_1600_8x8, cpu_classes=(DerivO3CPU, DerivO3CPU)
  • mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU)
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/realview64-switcheroo-timing.py
b/tests/gem5/configs/realview64-switcheroo-timing.py
index b94c657..4ccce5d 100644
--- a/tests/gem5/configs/realview64-switcheroo-timing.py
+++ b/tests/gem5/configs/realview64-switcheroo-timing.py
@@ -38,7 +38,8 @@
import switcheroo

root = LinuxArmFSSwitcheroo(

  • mem_class=DDR3_1600_8x8, cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
  • mem_class=DDR3_1600_8x8,
  • cpu_classes=(ArmTimingSimpleCPU, ArmTimingSimpleCPU),
    ).create_root()

Setup a custom test method that uses the switcheroo tester that

diff --git a/tests/gem5/configs/riscv_boot_exit_run.py
b/tests/gem5/configs/riscv_boot_exit_run.py
index 1636fac..4424868 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -66,7 +66,7 @@
"-m",
"--mem-system",
type=str,

  • choices=("classic", "mi_example"),
  • choices=("classic", "mesi_two_level"),
    required=True,
    help="The memory system.",
    )
    @@ -110,13 +110,21 @@
    cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
    l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
    )
    -elif args.mem_system == "mi_example":
  • from gem5.components.cachehierarchies.ruby.mi_example_cache_hierarchy
    import (
  •    MIExampleCacheHierarchy,
    

+elif args.mem_system == "mesi_two_level":

  • from
    gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import
    (
  •    MESITwoLevelCacheHierarchy,
    )
    
    # Setup the cache hierarchy.
    
  • cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8)
  • cache_hierarchy = MESITwoLevelCacheHierarchy(

  •    l1d_size="16kB",
    
  •    l1d_assoc=8,
    
  •    l1i_size="16kB",
    
  •    l1i_assoc=8,
    
  •    l2_size="256kB",
    
  •    l2_assoc=16,
    
  •    num_l2_banks=1,
    
  • )

    Setup the system memory.

    python_module = "gem5.components.memory"
    diff --git a/tests/gem5/configs/switcheroo.py
    b/tests/gem5/configs/switcheroo.py
    index f56ab96..5f38543 100644
    --- a/tests/gem5/configs/switcheroo.py
    +++ b/tests/gem5/configs/switcheroo.py
    @@ -38,7 +38,7 @@
    from m5.objects import *

    m5.util.addToPath("../configs/")
    -from common.Caches import *
    +from base_caches import *

    class Sequential:
    diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py
    index 80544e1..fb528e5 100644
    --- a/tests/gem5/cpu_tests/run.py
    +++ b/tests/gem5/cpu_tests/run.py
    @@ -29,8 +29,6 @@
    import argparse

    import m5
    -from gem5.isas import ISA
    -from gem5.runtime import get_runtime_isa
    from m5.objects import *

@@ -99,27 +97,25 @@
latency = "1ns"

-if get_runtime_isa() == ISA.X86:

  • valid_cpu = {
  •    "AtomicSimpleCPU": AtomicSimpleCPU,
    
  •    "TimingSimpleCPU": TimingSimpleCPU,
    
  •    "DerivO3CPU": DerivO3CPU,
    
  • }
    -else:
  • valid_cpu = {
  •    "AtomicSimpleCPU": AtomicSimpleCPU,
    
  •    "TimingSimpleCPU": TimingSimpleCPU,
    
  •    "MinorCPU": MinorCPU,
    
  •    "DerivO3CPU": DerivO3CPU,
    
  • }
    +valid_cpu = {
  • "X86AtomicSimpleCPU": X86AtomicSimpleCPU,
  • "X86TimingSimpleCPU": X86TimingSimpleCPU,
  • "X86DerivO3CPU": X86O3CPU,
  • "ArmAtomicSimpleCPU": ArmAtomicSimpleCPU,
  • "ArmTimingSimpleCPU": ArmTimingSimpleCPU,
  • "ArmMinorCPU": ArmMinorCPU,
  • "ArmDerivO3CPU": ArmO3CPU,
  • "RiscvAtomicSimpleCPU": RiscvAtomicSimpleCPU,
  • "RiscvTimingSimpleCPU": RiscvTimingSimpleCPU,
  • "RiscvMinorCPU": RiscvMinorCPU,
  • "RiscvDerivO3CPU": RiscvO3CPU,
    +}

valid_mem = {"SimpleMemory": MySimpleMemory, "DDR3_1600_8x8":
DDR3_1600_8x8}

parser = argparse.ArgumentParser()
parser.add_argument("binary", type=str)
-parser.add_argument(

  • "--cpu", choices=valid_cpu.keys(), default="TimingSimpleCPU"
    -)
    +parser.add_argument("--cpu")
    parser.add_argument("--mem", choices=valid_mem.keys(),
    default="SimpleMemory")

args = parser.parse_args()
@@ -132,14 +128,22 @@
system.clk_domain.clock = "1GHz"
system.clk_domain.voltage_domain = VoltageDomain()

-if args.cpu != "AtomicSimpleCPU":
+if args.cpu not in (

  • "X86AtomicSimpleCPU",
  • "ArmAtomicSimpleCPU",
  • "RiscvAtomicSimpleCPU",
    +):
    system.mem_mode = "timing"

system.mem_ranges = [AddrRange("512MB")]

system.cpu = valid_cpuargs.cpu

-if args.cpu == "AtomicSimpleCPU":
+if args.cpu in (

  • "X86AtomicSimpleCPU",
  • "ArmAtomicSimpleCPU",
  • "RiscvAtomicSimpleCPU",
    +):
    system.membus = SystemXBar()
    system.cpu.icache_port = system.membus.cpu_side_ports
    system.cpu.dcache_port = system.membus.cpu_side_ports
    @@ -157,7 +161,7 @@
    system.l2cache.connectMemSideBus(system.membus)

system.cpu.createInterruptController()
-if get_runtime_isa() == ISA.X86:
+if args.cpu in
("X86AtomicSimpleCPU", "X86TimingSimpleCPU", "X86DerivO3CPU"):
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports
diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index fe03f18..bbdb492 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -47,21 +47,21 @@

valid_isas = {
constants.vega_x86_tag: (

  •    "AtomicSimpleCPU",
    
  •    "TimingSimpleCPU",
    
  •    "DerivO3CPU",
    
  •    "X86AtomicSimpleCPU",
    
  •    "X86TimingSimpleCPU",
    
  •    "X86DerivO3CPU",
    ),
    constants.arm_tag: (
    
  •    "AtomicSimpleCPU",
    
  •    "TimingSimpleCPU",
    
  •    "MinorCPU",
    
  •    "DerivO3CPU",
    
  •    "ArmAtomicSimpleCPU",
    
  •    "ArmTimingSimpleCPU",
    
  •    "ArmMinorCPU",
    
  •    "ArmDerivO3CPU",
    ),
    constants.riscv_tag: (
    
  •    "AtomicSimpleCPU",
    
  •    "TimingSimpleCPU",
    
  •    "MinorCPU",
    
  •    "DerivO3CPU",
    
  •    "RiscvAtomicSimpleCPU",
    
  •    "RiscvTimingSimpleCPU",
    
  •    "RiscvMinorCPU",
    
  •    "RiscvDerivO3CPU",
    ),
    
    }

@@ -92,6 +92,6 @@
verifiers=verifiers,
config=joinpath(getcwd(), "run.py"),
config_args=["--cpu={}".format(cpu), binary],

  •            valid_isas=(isa,),
    
  •            valid_isas=(constants.all_compiled_tag,),
                fixtures=[workload_binary],
            )
    

diff --git a/tests/gem5/dram-lowp/test_dram_lowp.py
b/tests/gem5/dram-lowp/test_dram_lowp.py
index 4554e78..2e146bb 100644
--- a/tests/gem5/dram-lowp/test_dram_lowp.py
+++ b/tests/gem5/dram-lowp/test_dram_lowp.py
@@ -34,7 +34,7 @@
verifiers=verifiers,

config=joinpath(config.base_dir, "configs", "dram", "low_power_sweep.py"),
config_args=["-p", "close_adaptive", "-r", "2"],

  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    )

@@ -44,6 +44,6 @@
verifiers=verifiers,

config=joinpath(config.base_dir, "configs", "dram", "low_power_sweep.py"),
config_args=["-p", "open_adaptive", "-r", "2"],

  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    )
    diff --git a/tests/gem5/fs/linux/arm/test.py
    b/tests/gem5/fs/linux/arm/test.py
    index baccbd3..dff2e74 100644
    --- a/tests/gem5/fs/linux/arm/test.py
    +++ b/tests/gem5/fs/linux/arm/test.py
    @@ -134,7 +134,7 @@
    verifiers=verifier_list(name),  # Add basic stat verifiers
    config=joinpath(filepath, "run.py"),
    config_args=args,
  •    valid_isas=(constants.arm_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        length=constants.quick_tag,
        valid_hosts=valid_hosts,
        fixtures=(arm_fs_binaries,),
    

@@ -152,7 +152,7 @@
verifiers=verifier_list(name),  # TODO: Add basic stat verifiers
config=joinpath(filepath, "run.py"),
config_args=args,

  •    valid_isas=(constants.arm_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        length=constants.long_tag,
        fixtures=(arm_fs_binaries,),
        uses_kvm=name in arm_fs_kvm_tests,
    

diff --git a/tests/gem5/gem5-resources/test_download_resources.py
b/tests/gem5/gem5-resources/test_download_resources.py
index 55b57db..c0efc8b 100644
--- a/tests/gem5/gem5-resources/test_download_resources.py
+++ b/tests/gem5/gem5-resources/test_download_resources.py
@@ -41,6 +41,6 @@
config.base_dir, "tests", "gem5", "configs", "download_check.py"
),
config_args=["--download-directory", resource_path],

  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.very_long_tag,
    )
    diff --git
    a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
    b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
    index ddb41bb..ae814cb 100644
    --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
    +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
    @@ -45,7 +45,7 @@

config.base_dir, "configs", "example", "gem5_library", "arm-hello.py"
),
config_args=[],

  • valid_isas=(constants.arm_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.quick_tag,
    )
    @@ -63,7 +63,7 @@
    "riscv-hello-save-checkpoint.py",
    ),
    config_args=[],
  • valid_isas=(constants.riscv_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.quick_tag,
    )
    @@ -81,7 +81,7 @@
    "riscv-hello-restore-checkpoint.py",
    ),
    config_args=[],
  • valid_isas=(constants.riscv_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.quick_tag,
    )
    @@ -101,7 +101,7 @@
    "x86-ubuntu-run-with-kvm.py",
    ),
    config_args=[],
  •    valid_isas=(constants.x86_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        valid_hosts=(constants.host_x86_64_tag,),
        length=constants.long_tag,
        uses_kvm=True,
    

@@ -119,7 +119,7 @@
"x86-ubuntu-run.py",
),
config_args=[],

  • valid_isas=(constants.x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.long_tag,
    )
    @@ -139,7 +139,7 @@
    "x86-parsec-benchmarks.py",
    ),
    config_args=["--benchmark", "blackscholes", "--size", "simsmall"],
  •    valid_isas=(constants.x86_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        protocol="MESI_Two_Level",
        valid_hosts=(constants.host_x86_64_tag,),
        length=constants.long_tag,
    

@@ -168,7 +168,7 @@
"--ticks",
"5000000000",
],

  •    valid_isas=(constants.x86_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        protocol="MESI_Two_Level",
        valid_hosts=(constants.host_x86_64_tag,),
        length=constants.long_tag,
    

@@ -190,7 +190,7 @@
"x86-gapbs-benchmarks.py",
),

config_args=["--benchmark", "bfs", "--synthetic", "1", "--size", "1"],

  •    valid_isas=(constants.x86_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        protocol="MESI_Two_Level",
        valid_hosts=(constants.host_x86_64_tag,),
        length=constants.long_tag,
    

@@ -209,7 +209,7 @@
"riscv-ubuntu-run.py",
),
config_args=[],

  • valid_isas=(constants.riscv_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.long_tag,
    )
    @@ -222,7 +222,7 @@
    config.base_dir, "configs", "example", "lupv", "run_lupv.py"
    ),
    config_args=["timing", "1", "--max-ticks", "1000000000"],
  • valid_isas=(constants.riscv_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.long_tag,
    )
    @@ -239,7 +239,7 @@
    "arm-ubuntu-boot-exit.py",
    ),
    config_args=[],
  • valid_isas=(constants.arm_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    valid_hosts=constants.supported_hosts,
    length=constants.long_tag,
    )
    diff --git a/tests/gem5/gpu/test_gpu_ruby_random.py
    b/tests/gem5/gpu/test_gpu_ruby_random.py
    index b244f18..e29ecf2 100644
    --- a/tests/gem5/gpu/test_gpu_ruby_random.py
    +++ b/tests/gem5/gpu/test_gpu_ruby_random.py
    @@ -53,7 +53,7 @@
    config_args=["--test-length", "50000", "--num-dmas", "0"],
    valid_isas=(constants.vega_x86_tag,),
    valid_hosts=constants.supported_hosts,
  • length=constants.quick_tag,
  • length=constants.long_tag,
    )

diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py
index 9e9239e..4dde9d6 100644
--- a/tests/gem5/insttest_se/test.py
+++ b/tests/gem5/insttest_se/test.py
@@ -62,6 +62,6 @@
resource_path,
"sparc",
],

  •            valid_isas=(isa,),
    
  •            valid_isas=(constants.all_compiled_tag,),
                length=constants.long_tag,
            )
    

diff --git a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
index 6dcb0c2..7467c02 100644
--- a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
+++ b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py
@@ -53,13 +53,13 @@

  if mem_system == "mesi_two_level":
      protocol_to_use = None
  •    isa_to_use = constants.x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    elif mem_system == "mi_example":
        protocol_to_use = "MI_example"
        isa_to_use = constants.x86_tag
    else:
        protocol_to_use = None
    
  •    isa_to_use = constants.vega_x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    
    gem5_verify_config(
        name=name,
    

diff --git a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
index 3f1ee9b..222c26b 100644
--- a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
+++ b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py
@@ -53,13 +53,13 @@

  if mem_system == "mesi_two_level":
      protocol_to_use = None
  •    isa_to_use = constants.x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    elif mem_system == "mi_example":
        protocol_to_use = "MI_example"
        isa_to_use = constants.x86_tag
    else:
        protocol_to_use = None
    
  •    isa_to_use = constants.vega_x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    
    gem5_verify_config(
        name=name,
    

diff --git a/tests/gem5/learning_gem5/part1_test.py
b/tests/gem5/learning_gem5/part1_test.py
index 5032fbe..5e44b0f 100644
--- a/tests/gem5/learning_gem5/part1_test.py
+++ b/tests/gem5/learning_gem5/part1_test.py
@@ -35,11 +35,25 @@
config=joinpath(config_path, "simple.py"),
config_args=[],
length=constants.quick_tag,

  • valid_isas=(
  •    constants.vega_x86_tag,
    
  •    constants.riscv_tag,
    
  •    constants.arm_tag,
    
  • ),
  • valid_isas=(constants.all_compiled_tag,),
    +)

+gem5_verify_config(

  • name="simple_test_arm",
  • verifiers=(),
  • config=joinpath(config_path, "simple-arm.py"),
  • config_args=[],
  • length=constants.quick_tag,
  • valid_isas=(constants.all_compiled_tag,),
    +)

+gem5_verify_config(

  • name="simple_test_riscv",
  • verifiers=(),
  • config=joinpath(config_path, "simple-riscv.py"),
  • config_args=[],
  • length=constants.quick_tag,
  • valid_isas=(constants.all_compiled_tag,),
    )

The "quick" two level tests.

@@ -49,9 +63,5 @@
config=joinpath(config_path, "two_level.py"),
config_args=[],
length=constants.quick_tag,

  • valid_isas=(
  •    constants.vega_x86_tag,
    
  •    constants.riscv_tag,
    
  •    constants.arm_tag,
    
  • ),
  • valid_isas=(constants.all_compiled_tag,),
    )
    diff --git a/tests/gem5/learning_gem5/part2_test.py
    b/tests/gem5/learning_gem5/part2_test.py
    index 39792fb..916bdfd 100644
    --- a/tests/gem5/learning_gem5/part2_test.py
    +++ b/tests/gem5/learning_gem5/part2_test.py
    @@ -35,7 +35,7 @@
    verifiers=(get_verifier("simple"),),
    config=joinpath(config_path, "run_simple.py"),
    config_args=[],
  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    )

gem5_verify_config(
@@ -43,7 +43,7 @@
verifiers=(get_verifier("hello_goodbye"),),
config=joinpath(config_path, "hello_goodbye.py"),
config_args=[],

  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    )

gem5_verify_config(
@@ -52,7 +52,7 @@
config=joinpath(config_path, "simple_memobj.py"),
config_args=[],
# note: by default the above script uses x86

  • valid_isas=(constants.vega_x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    )

gem5_verify_config(
@@ -61,7 +61,7 @@
config=joinpath(config_path, "simple_cache.py"),
config_args=[],
# note: by default the above script uses x86

  • valid_isas=(constants.vega_x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    )

Note: for simple memobj and simple cache I want to use the traffic

generator
diff --git a/tests/gem5/learning_gem5/part3_test.py
b/tests/gem5/learning_gem5/part3_test.py
index d5a9d71..668f57d 100644
--- a/tests/gem5/learning_gem5/part3_test.py
+++ b/tests/gem5/learning_gem5/part3_test.py
@@ -40,9 +40,9 @@
config_args=[],
protocol="MSI",
# Currently only x86 has the threads test

  • valid_isas=(constants.x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),

    dynamically linked

  • valid_hosts=constants.target_host[constants.x86_tag],
  • valid_hosts=(constants.x86_tag,),
    length=constants.long_tag,
    )

@@ -53,6 +53,6 @@
config_args=[],
protocol="MSI",
# Currently only x86 has the threads test

  • valid_isas=(constants.x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.long_tag,
    )
    diff --git a/tests/gem5/m5_util/test_exit.py
    b/tests/gem5/m5_util/test_exit.py
    index e34e4ef..b79a8fad 100644
    --- a/tests/gem5/m5_util/test_exit.py
    +++ b/tests/gem5/m5_util/test_exit.py
    @@ -66,5 +66,5 @@
    resource_path,
    "x86",
    ],
  • valid_isas=(constants.vega_x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    )
    diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py
    b/tests/gem5/m5threads_test_atomic/atomic_system.py
    index 03c27a7..b7bd67d 100644
    --- a/tests/gem5/m5threads_test_atomic/atomic_system.py
    +++ b/tests/gem5/m5threads_test_atomic/atomic_system.py
    @@ -50,11 +50,11 @@

if args.cpu_type == "DerivO3CPU":
root.system.cpu = [

  •    DerivO3CPU(cpu_id=i) for i in range(int(args.num_cores))
    
  •    SparcDerivO3CPU(cpu_id=i) for i in range(int(args.num_cores))
    ]
    
    elif args.cpu_type == "TimingSimpleCPU":
    root.system.cpu = [
  •    TimingSimpleCPU(cpu_id=i) for i in range(int(args.num_cores))
    
  •    SparcTimingSimpleCPU(cpu_id=i) for i in range(int(args.num_cores))
    ]
    
    else:
    print("ERROR: CPU Type '" + args.cpu_type + "' not supported")
    diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
    index c2cf846..d76463b 100644
    --- a/tests/gem5/memory/test.py
    +++ b/tests/gem5/memory/test.py
    @@ -37,6 +37,7 @@
    config=joinpath(getcwd(), "simple-run.py"),
    config_args=[],
    valid_isas=(constants.null_tag,),
  • length=constants.long_tag,
    )

simple_mem_params = [
@@ -57,6 +58,7 @@
config=joinpath(getcwd(), "simple-run.py"),
config_args=args,
valid_isas=(constants.null_tag,),

  •    length=constants.long_tag,
    )  # This tests for validity as well as performance
    

    gem5_verify_config(
    @@ -65,6 +67,7 @@
    config=joinpath(getcwd(), "memtest-run.py"),
    config_args=[],
    valid_isas=(constants.null_tag,),

  • length=constants.long_tag,
    )

null_tests = [
@@ -132,4 +135,5 @@
config_args=args,
valid_isas=(constants.null_tag,),
valid_hosts=constants.supported_hosts,

  •    length=constants.long_tag,
    )
    

diff --git a/tests/gem5/multi_isa/test_multi_isa.py
b/tests/gem5/multi_isa/test_multi_isa.py
index 4d7a18c..2c6a96c 100644
--- a/tests/gem5/multi_isa/test_multi_isa.py
+++ b/tests/gem5/multi_isa/test_multi_isa.py
@@ -36,15 +36,6 @@
"riscv": constants.riscv_tag,
}

-length_map = {

  • "sparc": constants.long_tag,
  • "mips": constants.long_tag,
  • "null": constants.quick_tag,
  • "arm": constants.quick_tag,
  • "x86": constants.quick_tag,
  • "power": constants.long_tag,
  • "riscv": constants.long_tag,
    -}

for isa in isa_map.keys():
gem5_verify_config(
@@ -57,7 +48,7 @@
config_args=["-e", isa],
valid_isas=(isa_map[isa],),
valid_hosts=constants.supported_hosts,

  •    length=length_map[isa],
    
  •    length=constants.long_tag,
    )
    
    gem5_verify_config(
    

@@ -74,7 +65,7 @@
config_args=["-e", isa],
valid_isas=(isa_map[isa],),
valid_hosts=constants.supported_hosts,

  •    length=length_map[isa],
    
  •    length=constants.long_tag,
    )
    
    if isa != "null":
    

@@ -94,5 +85,5 @@
config_args=["-e", isa],
valid_isas=(constants.all_compiled_tag,),
valid_hosts=constants.supported_hosts,

  •        length=constants.long_tag,
    
  •        length=constants.quick_tag,
        )
    

diff --git a/tests/gem5/parsec-benchmarks/test_parsec.py
b/tests/gem5/parsec-benchmarks/test_parsec.py
index 86cfa7c..11735ab 100644
--- a/tests/gem5/parsec-benchmarks/test_parsec.py
+++ b/tests/gem5/parsec-benchmarks/test_parsec.py
@@ -75,7 +75,7 @@
"--resource-directory",
resource_path,
],

  •    valid_isas=(constants.x86_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        valid_hosts=(constants.host_x86_64_tag,),
        length=length,
        uses_kvm=True,
    

diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py
b/tests/gem5/riscv-boot-tests/test_linux_boot.py
index 5ac7bec..5ba4fa5 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -86,7 +86,7 @@
"riscv_boot_exit_run.py",
),
config_args=config_args,

  •    valid_isas=(constants.riscv_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        valid_hosts=constants.supported_hosts,
        length=length,
    )
    

@@ -133,7 +133,7 @@
test_boot(
cpu="minor",
num_cpus=1,

  • cache_type="mi_example",
  • cache_type="mesi_two_level",
    memory_class="SingleChannelDDR3_2133",
    length=constants.quick_tag,
    to_tick=10000000000,
    @@ -142,7 +142,7 @@
    test_boot(
    cpu="minor",
    num_cpus=8,
  • cache_type="mi_example",
  • cache_type="mesi_two_level",
    memory_class="SingleChannelDDR3_2133",
    length=constants.quick_tag,
    to_tick=10000000000,
    @@ -152,7 +152,7 @@
    test_boot(
    cpu="timing",
    num_cpus=1,
  • cache_type="mi_example",
  • cache_type="mesi_two_level",
    memory_class="SingleChannelDDR4_2400",
    length=constants.quick_tag,
    to_tick=10000000000,
    @@ -179,7 +179,7 @@
    test_boot(
    cpu="timing",
    num_cpus=4,
  • cache_type="mi_example",
  • cache_type="mesi_two_level",
    memory_class="DualChannelDDR4_2400",
    length=constants.quick_tag,
    to_tick=10000000000,
    @@ -202,7 +202,7 @@

test_boot(

cpu="timing",

num_cpus=1,

-#    cache_type="mi_example",
+#    cache_type="mesi_two_level",

memory_class="SingleChannelLPDDR3_1600",

length=constants.long_tag,

)

@@ -210,7 +210,7 @@

test_boot(

cpu="timing",

num_cpus=4,

-#    cache_type="mi_example",
+#    cache_type="mesi_two_level",

memory_class="DualChannelDDR4_2400",

length=constants.long_tag,

)

@@ -226,7 +226,7 @@

test_boot(

cpu="o3",

num_cpus=8,

-#    cache_type="mi_example",
+#    cache_type="mesi_two_level",

memory_class="HBM2Stack",

length=constants.long_tag,

)

diff --git a/tests/gem5/se_mode/hello_se/test_hello_se.py
b/tests/gem5/se_mode/hello_se/test_hello_se.py
index a9dea82..1aaac4a 100644
--- a/tests/gem5/se_mode/hello_se/test_hello_se.py
+++ b/tests/gem5/se_mode/hello_se/test_hello_se.py
@@ -79,17 +79,6 @@
constants.sparc_tag: ("timing", "atomic"),
}

-# We only want to test x86, arm, and riscv on quick. Mips and sparc will be
-# left for long.
-os_length = {

  • constants.vega_x86_tag: constants.quick_tag,
  • constants.arm_tag: constants.quick_tag,
  • constants.mips_tag: constants.long_tag,
  • constants.riscv_tag: constants.quick_tag,
  • constants.sparc_tag: constants.long_tag,
    -}
  • if config.bin_path:
    resource_path = config.bin_path
    else:
    @@ -117,9 +106,9 @@
    isa_str_map[isa],
    ]
    + input,
  •    valid_isas=(isa,),
    
  •    valid_isas=(constants.all_compiled_tag,),
        valid_hosts=hosts,
    
  •    length=os_length[isa],
    
  •    length=constants.quick_tag,
    )
    

diff --git a/tests/gem5/se_mode/hello_se/test_se_multicore.py
b/tests/gem5/se_mode/hello_se/test_se_multicore.py
index cee84a6..55fc61f 100644
--- a/tests/gem5/se_mode/hello_se/test_se_multicore.py
+++ b/tests/gem5/se_mode/hello_se/test_se_multicore.py
@@ -51,6 +51,6 @@
"--resource-directory",
resource_path,
],

  • valid_isas=(constants.vega_x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.quick_tag,
    )
    diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py
    index 187e1e8..993534a 100644
    --- a/tests/gem5/stats/test_hdf5.py
    +++ b/tests/gem5/stats/test_hdf5.py
    @@ -94,5 +94,5 @@
    "arm",
    ],
    gem5_args=["--stats-file=h5://stats.h5"],
  •    valid_isas=(constants.arm_tag,),
    
  •    valid_isas=(constants.all_compiled_tag,),
    )
    

diff --git a/tests/gem5/stdlib/test_base_cpu_processor.py
b/tests/gem5/stdlib/test_base_cpu_processor.py
index d6b0561..cbc6767 100644
--- a/tests/gem5/stdlib/test_base_cpu_processor.py
+++ b/tests/gem5/stdlib/test_base_cpu_processor.py
@@ -40,7 +40,7 @@
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["x86-hello64-static", "timing", "x86", "-b"],

  • valid_isas=(constants.vega_x86_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.quick_tag,
    )

@@ -52,7 +52,7 @@
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["riscv-hello", "atomic", "riscv", "-b"],

  • valid_isas=(constants.riscv_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.quick_tag,
    )

@@ -64,6 +64,6 @@
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
),
config_args=["arm-hello64-static", "o3", "arm", "-b"],

  • valid_isas=(constants.arm_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.quick_tag,
    )
    diff --git a/tests/gem5/stdlib/test_requires.py
    b/tests/gem5/stdlib/test_requires.py
    index 7d3282c..a70ca6b 100644
    --- a/tests/gem5/stdlib/test_requires.py
    +++ b/tests/gem5/stdlib/test_requires.py
    @@ -39,9 +39,9 @@
    length_map = {
    "sparc": constants.long_tag,
    "mips": constants.long_tag,
  • "null": constants.quick_tag,
  • "arm": constants.quick_tag,
  • "x86": constants.quick_tag,
  • "null": constants.long_tag,
  • "arm": constants.long_tag,
  • "x86": constants.long_tag,
    "power": constants.long_tag,
    "riscv": constants.long_tag,
    }
    diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
    b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
    index 75d21dc..10e2bd2 100644
    --- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
    +++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
    @@ -42,18 +42,6 @@
    memory: str,
    *args,
    ) -> None:
  • protocol_map = {

  •    "NoCache": None,
    
  •    "PrivateL1": None,
    
  •    "PrivateL1PrivateL2": None,
    
  •    "MESITwoLevel": "MESI_Two_Level",
    
  • }

  • tag_map = {

  •    "NoCache": constants.quick_tag,
    
  •    "PrivateL1": constants.quick_tag,
    
  •    "PrivateL1PrivateL2": constants.quick_tag,
    
  •    "MESITwoLevel": constants.long_tag,
    
  • }

    name = (
        "test-memory-"
    

@@ -75,10 +63,9 @@
),
config_args=[generator, generator_cores, cache, module, memory]
+ list(args),

  •    valid_isas=(constants.null_tag,),
    
  •    protocol=protocol_map[cache],
    
  •    valid_isas=(constants.all_compiled_tag,),
        valid_hosts=constants.supported_hosts,
    
  •    length=tag_map[cache],
    
  •    length=constants.quick_tag,
    )
    

diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index be8010d..ecda2ff 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -64,13 +64,13 @@

  if mem_system == "mesi_two_level":
      protocol_to_use = None
  •    isa_to_use = constants.x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    elif mem_system == "mi_example":
        protocol_to_use = "MI_example"
        isa_to_use = constants.x86_tag
    else:
        protocol_to_use = None
    
  •    isa_to_use = constants.vega_x86_tag
    
  •    isa_to_use = constants.all_compiled_tag
    
    gem5_verify_config(
        name=name,
    

diff --git a/tests/pyunit/test_run.py b/tests/pyunit/test_run.py
index 0fc8e6c..76cd5f7 100644
--- a/tests/pyunit/test_run.py
+++ b/tests/pyunit/test_run.py
@@ -43,6 +43,6 @@
config=os.path.join(os.getcwd(), os.pardir, "run_pyunit.py"),
verifiers=(),
config_args=[],

  • valid_isas=(constants.null_tag,),
  • valid_isas=(constants.all_compiled_tag,),
    length=constants.quick_tag,
    )

--
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https://gem5-review.googlesource.com/c/public/gem5/+/63374?usp=email
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I533689ad6848233867bdba9e9a43bb5840ed65c7
Gerrit-Change-Number: 63374
Gerrit-PatchSet: 15
Gerrit-Owner: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Bobby Bruce bbruce@ucdavis.edu
Gerrit-Reviewer: Giacomo Travaglini giacomo.travaglini@arm.com
Gerrit-Reviewer: Jason Lowe-Power jason@lowepower.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-CC: Jason Lowe-Power power.jg@gmail.com
Gerrit-MessageType: merged

Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/63374?usp=email ) Change subject: tests: Update tests to use ALL/gem5.opt compilation ...................................................................... tests: Update tests to use ALL/gem5.opt compilation Where possible the gem5 tests have been updated to use the build/ALL/gem5.opt compilation. If a quick test requied a specific a ISA/protocol compilation they were moved to the long/nightly set. This means all the quick/kokoro tests are run with the build/ALL/gem5.opt compilation. The learning_gem5 tests have been updated to use ALL/gem5.opt. The equivilant examples on the website have been updated via: https://gem5-review.googlesource.com/c/public/gem5-website/+/63336 Change-Id: I533689ad6848233867bdba9e9a43bb5840ed65c7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63374 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> --- M configs/example/gem5_library/arm-ubuntu-boot-exit.py A configs/learning_gem5/part1/simple-arm.py A configs/learning_gem5/part1/simple-riscv.py M configs/learning_gem5/part1/simple.py M configs/learning_gem5/part1/two_level.py M configs/learning_gem5/part2/simple_cache.py M configs/learning_gem5/part2/simple_memobj.py M configs/learning_gem5/part3/msi_caches.py M configs/learning_gem5/part3/ruby_caches_MI_example.py M configs/learning_gem5/part3/simple_ruby.py M tests/gem5/asmtest/tests.py M tests/gem5/configs/arm_generic.py A tests/gem5/configs/base_caches.py M tests/gem5/configs/base_config.py M tests/gem5/configs/realview-minor.py M tests/gem5/configs/realview-simple-atomic-checkpoint.py M tests/gem5/configs/realview-simple-atomic-dual.py M tests/gem5/configs/realview-simple-atomic.py M tests/gem5/configs/realview-simple-timing-dual-ruby.py M tests/gem5/configs/realview-simple-timing-dual.py M tests/gem5/configs/realview-simple-timing-ruby.py M tests/gem5/configs/realview-simple-timing.py M tests/gem5/configs/realview-switcheroo-atomic.py M tests/gem5/configs/realview-switcheroo-full.py M tests/gem5/configs/realview-switcheroo-noncaching-timing.py M tests/gem5/configs/realview-switcheroo-o3.py M tests/gem5/configs/realview-switcheroo-timing.py M tests/gem5/configs/realview64-minor-dual.py M tests/gem5/configs/realview64-minor.py M tests/gem5/configs/realview64-o3-dual-ruby.py M tests/gem5/configs/realview64-simple-atomic-checkpoint.py M tests/gem5/configs/realview64-simple-atomic-dual.py M tests/gem5/configs/realview64-simple-atomic.py M tests/gem5/configs/realview64-simple-timing-dual-ruby.py M tests/gem5/configs/realview64-simple-timing-dual.py M tests/gem5/configs/realview64-simple-timing-ruby.py M tests/gem5/configs/realview64-simple-timing.py M tests/gem5/configs/realview64-switcheroo-atomic.py M tests/gem5/configs/realview64-switcheroo-full.py M tests/gem5/configs/realview64-switcheroo-o3.py M tests/gem5/configs/realview64-switcheroo-timing.py M tests/gem5/configs/riscv_boot_exit_run.py M tests/gem5/configs/switcheroo.py M tests/gem5/cpu_tests/run.py M tests/gem5/cpu_tests/test.py M tests/gem5/dram-lowp/test_dram_lowp.py M tests/gem5/fs/linux/arm/test.py M tests/gem5/gem5-resources/test_download_resources.py M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py M tests/gem5/gpu/test_gpu_ruby_random.py M tests/gem5/insttest_se/test.py M tests/gem5/kvm-fork-tests/test_kvm_fork_run.py M tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py M tests/gem5/learning_gem5/part1_test.py M tests/gem5/learning_gem5/part2_test.py M tests/gem5/learning_gem5/part3_test.py M tests/gem5/m5_util/test_exit.py M tests/gem5/m5threads_test_atomic/atomic_system.py M tests/gem5/memory/test.py M tests/gem5/multi_isa/test_multi_isa.py M tests/gem5/parsec-benchmarks/test_parsec.py M tests/gem5/riscv-boot-tests/test_linux_boot.py M tests/gem5/se_mode/hello_se/test_hello_se.py M tests/gem5/se_mode/hello_se/test_se_multicore.py M tests/gem5/stats/test_hdf5.py M tests/gem5/stdlib/test_base_cpu_processor.py M tests/gem5/stdlib/test_requires.py M tests/gem5/traffic_gen/test_memory_traffic_gen.py M tests/gem5/x86-boot-tests/test_linux_boot.py M tests/pyunit/test_run.py 70 files changed, 480 insertions(+), 225 deletions(-) Approvals: Bobby Bruce: Looks good to me, approved Giacomo Travaglini: Looks good to me, approved kokoro: Regressions pass diff --git a/configs/example/gem5_library/arm-ubuntu-boot-exit.py b/configs/example/gem5_library/arm-ubuntu-boot-exit.py index 69984a9..201fb23 100644 --- a/configs/example/gem5_library/arm-ubuntu-boot-exit.py +++ b/configs/example/gem5_library/arm-ubuntu-boot-exit.py @@ -76,7 +76,7 @@ # Here we setup the processor. We use a simple TIMING processor. The config # script was also tested with ATOMIC processor. -processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2) +processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2, isa=ISA.ARM) # The ArmBoard requires a `release` to be specified. This adds all the # extensions or features to the system. We are setting this to Armv8 diff --git a/configs/learning_gem5/part1/simple-arm.py b/configs/learning_gem5/part1/simple-arm.py new file mode 100644 index 0000000..62f7645 --- /dev/null +++ b/configs/learning_gem5/part1/simple-arm.py @@ -0,0 +1,78 @@ +# Copyright (c) 2015 Jason Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This is the ARM equivalent to `simple.py` (which is designed to run using the +X86 ISA). More detailed documentation can be found in `simple.py`. +""" + +import m5 +from m5.objects import * + +system = System() + +system.clk_domain = SrcClockDomain() +system.clk_domain.clock = "1GHz" +system.clk_domain.voltage_domain = VoltageDomain() + +system.mem_mode = "timing" +system.mem_ranges = [AddrRange("512MB")] +system.cpu = ArmTimingSimpleCPU() + +system.membus = SystemXBar() + +system.cpu.icache_port = system.membus.cpu_side_ports +system.cpu.dcache_port = system.membus.cpu_side_ports + +system.cpu.createInterruptController() + +system.mem_ctrl = MemCtrl() +system.mem_ctrl.dram = DDR3_1600_8x8() +system.mem_ctrl.dram.range = system.mem_ranges[0] +system.mem_ctrl.port = system.membus.mem_side_ports + +system.system_port = system.membus.cpu_side_ports + +thispath = os.path.dirname(os.path.realpath(__file__)) +binary = os.path.join( + thispath, + "../../../", + "tests/test-progs/hello/bin/arm/linux/hello", +) + +system.workload = SEWorkload.init_compatible(binary) + +process = Process() +process.cmd = [binary] +system.cpu.workload = process +system.cpu.createThreads() + +root = Root(full_system=False, system=system) +m5.instantiate() + +print("Beginning simulation!") +exit_event = m5.simulate() +print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause())) diff --git a/configs/learning_gem5/part1/simple-riscv.py b/configs/learning_gem5/part1/simple-riscv.py new file mode 100644 index 0000000..f05ca4a --- /dev/null +++ b/configs/learning_gem5/part1/simple-riscv.py @@ -0,0 +1,78 @@ +# Copyright (c) 2015 Jason Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This is the RISCV equivalent to `simple.py` (which is designed to run using the +X86 ISA). More detailed documentation can be found in `simple.py`. +""" + +import m5 +from m5.objects import * + +system = System() + +system.clk_domain = SrcClockDomain() +system.clk_domain.clock = "1GHz" +system.clk_domain.voltage_domain = VoltageDomain() + +system.mem_mode = "timing" +system.mem_ranges = [AddrRange("512MB")] +system.cpu = RiscvTimingSimpleCPU() + +system.membus = SystemXBar() + +system.cpu.icache_port = system.membus.cpu_side_ports +system.cpu.dcache_port = system.membus.cpu_side_ports + +system.cpu.createInterruptController() + +system.mem_ctrl = MemCtrl() +system.mem_ctrl.dram = DDR3_1600_8x8() +system.mem_ctrl.dram.range = system.mem_ranges[0] +system.mem_ctrl.port = system.membus.mem_side_ports + +system.system_port = system.membus.cpu_side_ports + +thispath = os.path.dirname(os.path.realpath(__file__)) +binary = os.path.join( + thispath, + "../../../", + "tests/test-progs/hello/bin/riscv/linux/hello", +) + +system.workload = SEWorkload.init_compatible(binary) + +process = Process() +process.cmd = [binary] +system.cpu.workload = process +system.cpu.createThreads() + +root = Root(full_system=False, system=system) +m5.instantiate() + +print("Beginning simulation!") +exit_event = m5.simulate() +print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause())) diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index f3570ed..e36cd78 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -1,4 +1,3 @@ -# -*- coding: utf-8 -*- # Copyright (c) 2015 Jason Power # All rights reserved. # @@ -33,6 +32,10 @@ IMPORTANT: If you modify this file, it's likely that the Learning gem5 book also needs to be updated. For now, email Jason <power.jg@gmail.com> +This script uses the X86 ISA. `simple-arm.py` and `simple-riscv.py` may be +referenced as examples of scripts which utilize the ARM and RISC-V ISAs +respectively. + """ # import the m5 (gem5) library created when gem5 is built @@ -40,8 +43,6 @@ # import all of the SimObjects from m5.objects import * -from gem5.isas import ISA -from gem5.runtime import get_runtime_isa # create the system we are going to simulate system = System() @@ -56,7 +57,9 @@ system.mem_ranges = [AddrRange("512MB")] # Create an address range # Create a simple CPU -system.cpu = TimingSimpleCPU() +# You can use ISA-specific CPU models for different workloads: +# `RiscvTimingSimpleCPU`, `ArmTimingSimpleCPU`. +system.cpu = X86TimingSimpleCPU() # Create a memory bus, a system crossbar, in this case system.membus = SystemXBar() @@ -68,12 +71,12 @@ # create the interrupt controller for the CPU and connect to the membus system.cpu.createInterruptController() -# For x86 only, make sure the interrupts are connected to the memory -# Note: these are directly connected to the memory bus and are not cached -if get_runtime_isa() == ISA.X86: - system.cpu.interrupts[0].pio = system.membus.mem_side_ports - system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports - system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports +# For X86 only we make sure the interrupts care connect to memory. +# Note: these are directly connected to the memory bus and are not cached. +# For other ISA you should remove the following three lines. +system.cpu.interrupts[0].pio = system.membus.mem_side_ports +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = MemCtrl() @@ -84,18 +87,14 @@ # Connect the system up to the membus system.system_port = system.membus.cpu_side_ports -# get ISA for the binary to run. -isa = get_runtime_isa() - -# Default to running 'hello', use the compiled ISA to find the binary -# grab the specific path to the binary +# Here we set the X86 "hello world" binary. With other ISAs you must specify +# workloads compiled to those ISAs. Other "hello world" binaries for other ISAs +# can be found in "tests/test-progs/hello". thispath = os.path.dirname(os.path.realpath(__file__)) binary = os.path.join( thispath, "../../../", - "tests/test-progs/hello/bin/", - isa.name.lower(), - "linux/hello", + "tests/test-progs/hello/bin/x86/linux/hello", ) system.workload = SEWorkload.init_compatible(binary) diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index 905e286..8aa7dd7 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -43,7 +43,6 @@ # import all of the SimObjects from m5.objects import * -from gem5.isas import ISA from gem5.runtime import get_runtime_isa # Add the common scripts to our path @@ -55,18 +54,13 @@ # import the SimpleOpts module from common import SimpleOpts -# get ISA for the default binary to run. This is mostly for simple testing -isa = get_runtime_isa() - # Default to running 'hello', use the compiled ISA to find the binary # grab the specific path to the binary thispath = os.path.dirname(os.path.realpath(__file__)) default_binary = os.path.join( thispath, "../../../", - "tests/test-progs/hello/bin/", - isa.name.lower(), - "linux/hello", + "tests/test-progs/hello/bin/x86/linux/hello", ) # Binary to execute @@ -88,7 +82,7 @@ system.mem_ranges = [AddrRange("512MB")] # Create an address range # Create a simple CPU -system.cpu = TimingSimpleCPU() +system.cpu = X86TimingSimpleCPU() # Create an L1 instruction and data cache system.cpu.icache = L1ICache(args) @@ -117,13 +111,9 @@ # create the interrupt controller for the CPU system.cpu.createInterruptController() - -# For x86 only, make sure the interrupts are connected to the memory -# Note: these are directly connected to the memory bus and are not cached -if isa == ISA.X86: - system.cpu.interrupts[0].pio = system.membus.mem_side_ports - system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports - system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports +system.cpu.interrupts[0].pio = system.membus.mem_side_ports +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports # Connect the system up to the membus system.system_port = system.membus.cpu_side_ports diff --git a/configs/learning_gem5/part2/simple_cache.py b/configs/learning_gem5/part2/simple_cache.py index 0a27979..4228956 100644 --- a/configs/learning_gem5/part2/simple_cache.py +++ b/configs/learning_gem5/part2/simple_cache.py @@ -50,7 +50,7 @@ system.mem_ranges = [AddrRange("512MB")] # Create an address range # Create a simple CPU -system.cpu = TimingSimpleCPU() +system.cpu = X86TimingSimpleCPU() # Create a memory bus, a coherent crossbar, in this case system.membus = SystemXBar() diff --git a/configs/learning_gem5/part2/simple_memobj.py b/configs/learning_gem5/part2/simple_memobj.py index ff4a2c9..20f4362 100644 --- a/configs/learning_gem5/part2/simple_memobj.py +++ b/configs/learning_gem5/part2/simple_memobj.py @@ -50,7 +50,7 @@ system.mem_ranges = [AddrRange("512MB")] # Create an address range # Create a simple CPU -system.cpu = TimingSimpleCPU() +system.cpu = X86TimingSimpleCPU() # Create the simple memory object system.memobj = SimpleMemobj() diff --git a/configs/learning_gem5/part3/msi_caches.py b/configs/learning_gem5/part3/msi_caches.py index 8567571..13b2a11 100644 --- a/configs/learning_gem5/part3/msi_caches.py +++ b/configs/learning_gem5/part3/msi_caches.py @@ -39,8 +39,6 @@ from m5.defines import buildEnv from m5.util import fatal, panic -from gem5.isas import ISA -from gem5.runtime import get_runtime_isa from m5.objects import * @@ -148,10 +146,10 @@ 1. The O3 model must keep the LSQ coherent with the caches 2. The x86 mwait instruction is built on top of coherence 3. The local exclusive monitor in ARM systems + + As this is an X86 simulation we return True. """ - if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM): - return True - return False + return True def connectQueues(self, ruby_system): """Connect all of the queues for this controller.""" diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py b/configs/learning_gem5/part3/ruby_caches_MI_example.py index 2374ca0..8c25a9b 100644 --- a/configs/learning_gem5/part3/ruby_caches_MI_example.py +++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py @@ -41,8 +41,6 @@ from m5.defines import buildEnv from m5.util import fatal, panic -from gem5.isas import ISA -from gem5.runtime import get_runtime_isa from m5.objects import * @@ -146,10 +144,10 @@ 1. The O3 model must keep the LSQ coherent with the caches 2. The x86 mwait instruction is built on top of coherence 3. The local exclusive monitor in ARM systems + + As this is an X86 simulation we return True. """ - if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM): - return True - return False + return True def connectQueues(self, ruby_system): """Connect all of the queues for this controller.""" diff --git a/configs/learning_gem5/part3/simple_ruby.py b/configs/learning_gem5/part3/simple_ruby.py index 7637935..b62a719 100644 --- a/configs/learning_gem5/part3/simple_ruby.py +++ b/configs/learning_gem5/part3/simple_ruby.py @@ -42,7 +42,6 @@ # import all of the SimObjects from m5.objects import * -from gem5.runtime import get_runtime_isa # Needed for running C++ threads m5.util.addToPath("../../") @@ -65,7 +64,7 @@ system.mem_ranges = [AddrRange("512MB")] # Create an address range # Create a pair of simple CPUs -system.cpu = [TimingSimpleCPU() for i in range(2)] +system.cpu = [X86TimingSimpleCPU() for i in range(2)] # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = MemCtrl() @@ -80,18 +79,13 @@ system.caches = MyCacheSystem() system.caches.setup(system, system.cpu, [system.mem_ctrl]) -# get ISA for the binary to run. -isa = get_runtime_isa() - # Run application and use the compiled ISA to find the binary # grab the specific path to the binary thispath = os.path.dirname(os.path.realpath(__file__)) binary = os.path.join( thispath, "../../../", - "tests/test-progs/threads/bin/", - isa.name.lower(), - "linux/threads", + "tests/test-progs/threads/bin/x86/linux/threads", ) # Create a process for a simple "multi-threaded" application diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py index cdaf556..b2a5992 100644 --- a/tests/gem5/asmtest/tests.py +++ b/tests/gem5/asmtest/tests.py @@ -192,6 +192,6 @@ "--resource-directory", resource_path, ], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, ) diff --git a/tests/gem5/configs/arm_generic.py b/tests/gem5/configs/arm_generic.py index 8408123..252ac6c 100644 --- a/tests/gem5/configs/arm_generic.py +++ b/tests/gem5/configs/arm_generic.py @@ -40,7 +40,7 @@ m5.util.addToPath("../configs/") from common import FSConfig -from common.Caches import * +from base_caches import * from base_config import * from common.cores.arm.O3_ARM_v7a import * from common.Benchmarks import SysConfig diff --git a/tests/gem5/configs/base_caches.py b/tests/gem5/configs/base_caches.py new file mode 100644 index 0000000..3b5f558 --- /dev/null +++ b/tests/gem5/configs/base_caches.py @@ -0,0 +1,85 @@ +# Copyright (c) 2012 ARM Limited +# Copyright (c) 2020 Barkhausen Institut +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects import * + +# Base implementations of L1, L2, IO and TLB-walker caches. There are +# used in the regressions and also as base components in the +# system-configuration scripts. The values are meant to serve as a +# starting point, and specific parameters can be overridden in the +# specific instantiations. + + +class L1Cache(Cache): + assoc = 2 + tag_latency = 2 + data_latency = 2 + response_latency = 2 + mshrs = 4 + tgts_per_mshr = 20 + + +class L1_ICache(L1Cache): + is_read_only = True + # Writeback clean lines as well + writeback_clean = True + + +class L1_DCache(L1Cache): + pass + + +class L2Cache(Cache): + assoc = 8 + tag_latency = 20 + data_latency = 20 + response_latency = 20 + mshrs = 20 + tgts_per_mshr = 12 + write_buffers = 8 + + +class IOCache(Cache): + assoc = 8 + tag_latency = 50 + data_latency = 50 + response_latency = 50 + mshrs = 20 + size = "1kB" + tgts_per_mshr = 12 diff --git a/tests/gem5/configs/base_config.py b/tests/gem5/configs/base_config.py index e190df1..22987d5 100644 --- a/tests/gem5/configs/base_config.py +++ b/tests/gem5/configs/base_config.py @@ -40,7 +40,7 @@ from m5.proxy import * from common import FSConfig from common import Options -from common.Caches import * +from base_caches import * from ruby import Ruby _have_kvm_support = "BaseKvmCPU" in globals() diff --git a/tests/gem5/configs/realview-minor.py b/tests/gem5/configs/realview-minor.py index cb85516..a635162 100644 --- a/tests/gem5/configs/realview-minor.py +++ b/tests/gem5/configs/realview-minor.py @@ -41,5 +41,5 @@ machine_type="VExpress_GEM5_V1", mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=MinorCPU, + cpu_class=ArmMinorCPU, ).create_root() diff --git a/tests/gem5/configs/realview-simple-atomic-checkpoint.py b/tests/gem5/configs/realview-simple-atomic-checkpoint.py index 9dbb48e..a60fd96 100644 --- a/tests/gem5/configs/realview-simple-atomic-checkpoint.py +++ b/tests/gem5/configs/realview-simple-atomic-checkpoint.py @@ -44,7 +44,7 @@ machine_type="VExpress_GEM5_V1", mem_mode="atomic", mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU, + cpu_class=ArmAtomicSimpleCPU, ).create_root() run_test = functools.partial(checkpoint.run_test, interval=0.2) diff --git a/tests/gem5/configs/realview-simple-atomic-dual.py b/tests/gem5/configs/realview-simple-atomic-dual.py index 7aded86..c02f872 100644 --- a/tests/gem5/configs/realview-simple-atomic-dual.py +++ b/tests/gem5/configs/realview-simple-atomic-dual.py @@ -41,6 +41,6 @@ machine_type="VExpress_GEM5_V1", mem_mode="atomic", mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU, + cpu_class=ArmAtomicSimpleCPU, num_cpus=2, ).create_root() diff --git a/tests/gem5/configs/realview-simple-atomic.py b/tests/gem5/configs/realview-simple-atomic.py index cb286dd..9c782ad 100644 --- a/tests/gem5/configs/realview-simple-atomic.py +++ b/tests/gem5/configs/realview-simple-atomic.py @@ -41,5 +41,5 @@ machine_type="VExpress_GEM5_V1", mem_mode="atomic", mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU, + cpu_class=ArmAtomicSimpleCPU, ).create_root() diff --git a/tests/gem5/configs/realview-simple-timing-dual-ruby.py b/tests/gem5/configs/realview-simple-timing-dual-ruby.py index cf4da18..741eded 100644 --- a/tests/gem5/configs/realview-simple-timing-dual-ruby.py +++ b/tests/gem5/configs/realview-simple-timing-dual-ruby.py @@ -41,7 +41,7 @@ machine_type="VExpress_GEM5_V1", mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, num_cpus=2, use_ruby=True, ).create_root() diff --git a/tests/gem5/configs/realview-simple-timing-dual.py b/tests/gem5/configs/realview-simple-timing-dual.py index b6c84e9..aaea9de 100644 --- a/tests/gem5/configs/realview-simple-timing-dual.py +++ b/tests/gem5/configs/realview-simple-timing-dual.py @@ -41,6 +41,6 @@ machine_type="VExpress_GEM5_V1", mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, num_cpus=2, ).create_root() diff --git a/tests/gem5/configs/realview-simple-timing-ruby.py b/tests/gem5/configs/realview-simple-timing-ruby.py index 4f7f73e..fcca943 100644 --- a/tests/gem5/configs/realview-simple-timing-ruby.py +++ b/tests/gem5/configs/realview-simple-timing-ruby.py @@ -41,6 +41,6 @@ machine_type="VExpress_GEM5_V1", mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, use_ruby=True, ).create_root() diff --git a/tests/gem5/configs/realview-simple-timing.py b/tests/gem5/configs/realview-simple-timing.py index 38cab57..2afbdd0 100644 --- a/tests/gem5/configs/realview-simple-timing.py +++ b/tests/gem5/configs/realview-simple-timing.py @@ -41,5 +41,5 @@ machine_type="VExpress_GEM5_V1", mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, ).create_root() diff --git a/tests/gem5/configs/realview-switcheroo-atomic.py b/tests/gem5/configs/realview-switcheroo-atomic.py index 1f64660..d2f2100 100644 --- a/tests/gem5/configs/realview-switcheroo-atomic.py +++ b/tests/gem5/configs/realview-switcheroo-atomic.py @@ -38,7 +38,8 @@ import switcheroo root = LinuxArmFSSwitcheroo( - mem_class=SimpleMemory, cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU) + mem_class=SimpleMemory, + cpu_classes=(ArmAtomicSimpleCPU, ArmAtomicSimpleCPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview-switcheroo-full.py b/tests/gem5/configs/realview-switcheroo-full.py index f3a7d03..6ed99a3 100644 --- a/tests/gem5/configs/realview-switcheroo-full.py +++ b/tests/gem5/configs/realview-switcheroo-full.py @@ -41,7 +41,12 @@ machine_type="VExpress_GEM5_V1", aarch64_kernel=False, mem_class=DDR3_1600_8x8, - cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU), + cpu_classes=( + ArmAtomicSimpleCPU, + ArmTimingSimpleCPU, + ArmMinorCPU, + ArmO3CPU, + ), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview-switcheroo-noncaching-timing.py b/tests/gem5/configs/realview-switcheroo-noncaching-timing.py index 9fbac61..cc77f44 100644 --- a/tests/gem5/configs/realview-switcheroo-noncaching-timing.py +++ b/tests/gem5/configs/realview-switcheroo-noncaching-timing.py @@ -38,7 +38,7 @@ import switcheroo root = LinuxArmFSSwitcheroo( - cpu_classes=(NonCachingSimpleCPU, TimingSimpleCPU) + cpu_classes=(ArmNonCachingSimpleCPU, ArmTimingSimpleCPU) ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview-switcheroo-o3.py b/tests/gem5/configs/realview-switcheroo-o3.py index 7eee6eb..fe3298f 100644 --- a/tests/gem5/configs/realview-switcheroo-o3.py +++ b/tests/gem5/configs/realview-switcheroo-o3.py @@ -41,7 +41,7 @@ aarch64_kernel=False, machine_type="VExpress_GEM5_V1", mem_class=DDR3_1600_8x8, - cpu_classes=(DerivO3CPU, DerivO3CPU), + cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview-switcheroo-timing.py b/tests/gem5/configs/realview-switcheroo-timing.py index eff1e80..5157da6 100644 --- a/tests/gem5/configs/realview-switcheroo-timing.py +++ b/tests/gem5/configs/realview-switcheroo-timing.py @@ -38,7 +38,8 @@ import switcheroo root = LinuxArmFSSwitcheroo( - mem_class=DDR3_1600_8x8, cpu_classes=(TimingSimpleCPU, TimingSimpleCPU) + mem_class=DDR3_1600_8x8, + cpu_classes=(ArmTimingSimpleCPU, ArmTimingSimpleCPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-minor-dual.py b/tests/gem5/configs/realview64-minor-dual.py index f067170..aed5d83 100644 --- a/tests/gem5/configs/realview64-minor-dual.py +++ b/tests/gem5/configs/realview64-minor-dual.py @@ -37,5 +37,8 @@ from arm_generic import * root = LinuxArmFSSystem( - mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=MinorCPU, num_cpus=2 + mem_mode="timing", + mem_class=DDR3_1600_8x8, + cpu_class=ArmMinorCPU, + num_cpus=2, ).create_root() diff --git a/tests/gem5/configs/realview64-minor.py b/tests/gem5/configs/realview64-minor.py index d1c6d93..7bad3c5 100644 --- a/tests/gem5/configs/realview64-minor.py +++ b/tests/gem5/configs/realview64-minor.py @@ -37,5 +37,5 @@ from arm_generic import * root = LinuxArmFSSystemUniprocessor( - mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=MinorCPU + mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmMinorCPU ).create_root() diff --git a/tests/gem5/configs/realview64-o3-dual-ruby.py b/tests/gem5/configs/realview64-o3-dual-ruby.py index 97e0090..a4bffe9 100644 --- a/tests/gem5/configs/realview64-o3-dual-ruby.py +++ b/tests/gem5/configs/realview64-o3-dual-ruby.py @@ -39,7 +39,7 @@ root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=O3CPU, + cpu_class=ArmO3CPU, num_cpus=2, enable_dvm=True, use_ruby=True, diff --git a/tests/gem5/configs/realview64-simple-atomic-checkpoint.py b/tests/gem5/configs/realview64-simple-atomic-checkpoint.py index c595037..fa73a0e 100644 --- a/tests/gem5/configs/realview64-simple-atomic-checkpoint.py +++ b/tests/gem5/configs/realview64-simple-atomic-checkpoint.py @@ -40,7 +40,7 @@ import checkpoint root = LinuxArmFSSystemUniprocessor( - mem_mode="atomic", mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU + mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU ).create_root() run_test = functools.partial( diff --git a/tests/gem5/configs/realview64-simple-atomic-dual.py b/tests/gem5/configs/realview64-simple-atomic-dual.py index 26ba53a..19cf751 100644 --- a/tests/gem5/configs/realview64-simple-atomic-dual.py +++ b/tests/gem5/configs/realview64-simple-atomic-dual.py @@ -39,6 +39,6 @@ root = LinuxArmFSSystem( mem_mode="atomic", mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU, + cpu_class=ArmAtomicSimpleCPU, num_cpus=2, ).create_root() diff --git a/tests/gem5/configs/realview64-simple-atomic.py b/tests/gem5/configs/realview64-simple-atomic.py index f9d30a4..299dd7b 100644 --- a/tests/gem5/configs/realview64-simple-atomic.py +++ b/tests/gem5/configs/realview64-simple-atomic.py @@ -37,5 +37,5 @@ from arm_generic import * root = LinuxArmFSSystemUniprocessor( - mem_mode="atomic", mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU + mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU ).create_root() diff --git a/tests/gem5/configs/realview64-simple-timing-dual-ruby.py b/tests/gem5/configs/realview64-simple-timing-dual-ruby.py index 991ed14..96ad963 100644 --- a/tests/gem5/configs/realview64-simple-timing-dual-ruby.py +++ b/tests/gem5/configs/realview64-simple-timing-dual-ruby.py @@ -39,7 +39,7 @@ root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, num_cpus=2, use_ruby=True, ).create_root() diff --git a/tests/gem5/configs/realview64-simple-timing-dual.py b/tests/gem5/configs/realview64-simple-timing-dual.py index 1e658df..8b62cd3 100644 --- a/tests/gem5/configs/realview64-simple-timing-dual.py +++ b/tests/gem5/configs/realview64-simple-timing-dual.py @@ -39,6 +39,6 @@ root = LinuxArmFSSystem( mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, num_cpus=2, ).create_root() diff --git a/tests/gem5/configs/realview64-simple-timing-ruby.py b/tests/gem5/configs/realview64-simple-timing-ruby.py index 8ed0287..f602453 100644 --- a/tests/gem5/configs/realview64-simple-timing-ruby.py +++ b/tests/gem5/configs/realview64-simple-timing-ruby.py @@ -39,6 +39,6 @@ root = LinuxArmFSSystemUniprocessor( mem_mode="timing", mem_class=DDR3_1600_8x8, - cpu_class=TimingSimpleCPU, + cpu_class=ArmTimingSimpleCPU, use_ruby=True, ).create_root() diff --git a/tests/gem5/configs/realview64-simple-timing.py b/tests/gem5/configs/realview64-simple-timing.py index 5c96506..6897f3b 100644 --- a/tests/gem5/configs/realview64-simple-timing.py +++ b/tests/gem5/configs/realview64-simple-timing.py @@ -37,5 +37,5 @@ from arm_generic import * root = LinuxArmFSSystemUniprocessor( - mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=TimingSimpleCPU + mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmTimingSimpleCPU ).create_root() diff --git a/tests/gem5/configs/realview64-switcheroo-atomic.py b/tests/gem5/configs/realview64-switcheroo-atomic.py index 12e57ed..c2f67f0 100644 --- a/tests/gem5/configs/realview64-switcheroo-atomic.py +++ b/tests/gem5/configs/realview64-switcheroo-atomic.py @@ -38,7 +38,8 @@ import switcheroo root = LinuxArmFSSwitcheroo( - mem_class=SimpleMemory, cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU) + mem_class=SimpleMemory, + cpu_classes=(ArmAtomicSimpleCPU, ArmAtomicSimpleCPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-switcheroo-full.py b/tests/gem5/configs/realview64-switcheroo-full.py index 0685255..abc96f9 100644 --- a/tests/gem5/configs/realview64-switcheroo-full.py +++ b/tests/gem5/configs/realview64-switcheroo-full.py @@ -39,7 +39,12 @@ root = LinuxArmFSSwitcheroo( mem_class=DDR3_1600_8x8, - cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, MinorCPU, DerivO3CPU), + cpu_classes=( + ArmAtomicSimpleCPU, + ArmTimingSimpleCPU, + ArmMinorCPU, + ArmDerivO3CPU, + ), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-switcheroo-o3.py b/tests/gem5/configs/realview64-switcheroo-o3.py index 833e6a4..ddfc73a 100644 --- a/tests/gem5/configs/realview64-switcheroo-o3.py +++ b/tests/gem5/configs/realview64-switcheroo-o3.py @@ -38,7 +38,7 @@ import switcheroo root = LinuxArmFSSwitcheroo( - mem_class=DDR3_1600_8x8, cpu_classes=(DerivO3CPU, DerivO3CPU) + mem_class=DDR3_1600_8x8, cpu_classes=(ArmDerivO3CPU, ArmDerivO3CPU) ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/realview64-switcheroo-timing.py b/tests/gem5/configs/realview64-switcheroo-timing.py index b94c657..4ccce5d 100644 --- a/tests/gem5/configs/realview64-switcheroo-timing.py +++ b/tests/gem5/configs/realview64-switcheroo-timing.py @@ -38,7 +38,8 @@ import switcheroo root = LinuxArmFSSwitcheroo( - mem_class=DDR3_1600_8x8, cpu_classes=(TimingSimpleCPU, TimingSimpleCPU) + mem_class=DDR3_1600_8x8, + cpu_classes=(ArmTimingSimpleCPU, ArmTimingSimpleCPU), ).create_root() # Setup a custom test method that uses the switcheroo tester that diff --git a/tests/gem5/configs/riscv_boot_exit_run.py b/tests/gem5/configs/riscv_boot_exit_run.py index 1636fac..4424868 100644 --- a/tests/gem5/configs/riscv_boot_exit_run.py +++ b/tests/gem5/configs/riscv_boot_exit_run.py @@ -66,7 +66,7 @@ "-m", "--mem-system", type=str, - choices=("classic", "mi_example"), + choices=("classic", "mesi_two_level"), required=True, help="The memory system.", ) @@ -110,13 +110,21 @@ cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB" ) -elif args.mem_system == "mi_example": - from gem5.components.cachehierarchies.ruby.mi_example_cache_hierarchy import ( - MIExampleCacheHierarchy, +elif args.mem_system == "mesi_two_level": + from gem5.components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import ( + MESITwoLevelCacheHierarchy, ) # Setup the cache hierarchy. - cache_hierarchy = MIExampleCacheHierarchy(size="32KiB", assoc=8) + cache_hierarchy = MESITwoLevelCacheHierarchy( + l1d_size="16kB", + l1d_assoc=8, + l1i_size="16kB", + l1i_assoc=8, + l2_size="256kB", + l2_assoc=16, + num_l2_banks=1, + ) # Setup the system memory. python_module = "gem5.components.memory" diff --git a/tests/gem5/configs/switcheroo.py b/tests/gem5/configs/switcheroo.py index f56ab96..5f38543 100644 --- a/tests/gem5/configs/switcheroo.py +++ b/tests/gem5/configs/switcheroo.py @@ -38,7 +38,7 @@ from m5.objects import * m5.util.addToPath("../configs/") -from common.Caches import * +from base_caches import * class Sequential: diff --git a/tests/gem5/cpu_tests/run.py b/tests/gem5/cpu_tests/run.py index 80544e1..fb528e5 100644 --- a/tests/gem5/cpu_tests/run.py +++ b/tests/gem5/cpu_tests/run.py @@ -29,8 +29,6 @@ import argparse import m5 -from gem5.isas import ISA -from gem5.runtime import get_runtime_isa from m5.objects import * @@ -99,27 +97,25 @@ latency = "1ns" -if get_runtime_isa() == ISA.X86: - valid_cpu = { - "AtomicSimpleCPU": AtomicSimpleCPU, - "TimingSimpleCPU": TimingSimpleCPU, - "DerivO3CPU": DerivO3CPU, - } -else: - valid_cpu = { - "AtomicSimpleCPU": AtomicSimpleCPU, - "TimingSimpleCPU": TimingSimpleCPU, - "MinorCPU": MinorCPU, - "DerivO3CPU": DerivO3CPU, - } +valid_cpu = { + "X86AtomicSimpleCPU": X86AtomicSimpleCPU, + "X86TimingSimpleCPU": X86TimingSimpleCPU, + "X86DerivO3CPU": X86O3CPU, + "ArmAtomicSimpleCPU": ArmAtomicSimpleCPU, + "ArmTimingSimpleCPU": ArmTimingSimpleCPU, + "ArmMinorCPU": ArmMinorCPU, + "ArmDerivO3CPU": ArmO3CPU, + "RiscvAtomicSimpleCPU": RiscvAtomicSimpleCPU, + "RiscvTimingSimpleCPU": RiscvTimingSimpleCPU, + "RiscvMinorCPU": RiscvMinorCPU, + "RiscvDerivO3CPU": RiscvO3CPU, +} valid_mem = {"SimpleMemory": MySimpleMemory, "DDR3_1600_8x8": DDR3_1600_8x8} parser = argparse.ArgumentParser() parser.add_argument("binary", type=str) -parser.add_argument( - "--cpu", choices=valid_cpu.keys(), default="TimingSimpleCPU" -) +parser.add_argument("--cpu") parser.add_argument("--mem", choices=valid_mem.keys(), default="SimpleMemory") args = parser.parse_args() @@ -132,14 +128,22 @@ system.clk_domain.clock = "1GHz" system.clk_domain.voltage_domain = VoltageDomain() -if args.cpu != "AtomicSimpleCPU": +if args.cpu not in ( + "X86AtomicSimpleCPU", + "ArmAtomicSimpleCPU", + "RiscvAtomicSimpleCPU", +): system.mem_mode = "timing" system.mem_ranges = [AddrRange("512MB")] system.cpu = valid_cpu[args.cpu]() -if args.cpu == "AtomicSimpleCPU": +if args.cpu in ( + "X86AtomicSimpleCPU", + "ArmAtomicSimpleCPU", + "RiscvAtomicSimpleCPU", +): system.membus = SystemXBar() system.cpu.icache_port = system.membus.cpu_side_ports system.cpu.dcache_port = system.membus.cpu_side_ports @@ -157,7 +161,7 @@ system.l2cache.connectMemSideBus(system.membus) system.cpu.createInterruptController() -if get_runtime_isa() == ISA.X86: +if args.cpu in ("X86AtomicSimpleCPU", "X86TimingSimpleCPU", "X86DerivO3CPU"): system.cpu.interrupts[0].pio = system.membus.mem_side_ports system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py index fe03f18..bbdb492 100644 --- a/tests/gem5/cpu_tests/test.py +++ b/tests/gem5/cpu_tests/test.py @@ -47,21 +47,21 @@ valid_isas = { constants.vega_x86_tag: ( - "AtomicSimpleCPU", - "TimingSimpleCPU", - "DerivO3CPU", + "X86AtomicSimpleCPU", + "X86TimingSimpleCPU", + "X86DerivO3CPU", ), constants.arm_tag: ( - "AtomicSimpleCPU", - "TimingSimpleCPU", - "MinorCPU", - "DerivO3CPU", + "ArmAtomicSimpleCPU", + "ArmTimingSimpleCPU", + "ArmMinorCPU", + "ArmDerivO3CPU", ), constants.riscv_tag: ( - "AtomicSimpleCPU", - "TimingSimpleCPU", - "MinorCPU", - "DerivO3CPU", + "RiscvAtomicSimpleCPU", + "RiscvTimingSimpleCPU", + "RiscvMinorCPU", + "RiscvDerivO3CPU", ), } @@ -92,6 +92,6 @@ verifiers=verifiers, config=joinpath(getcwd(), "run.py"), config_args=["--cpu={}".format(cpu), binary], - valid_isas=(isa,), + valid_isas=(constants.all_compiled_tag,), fixtures=[workload_binary], ) diff --git a/tests/gem5/dram-lowp/test_dram_lowp.py b/tests/gem5/dram-lowp/test_dram_lowp.py index 4554e78..2e146bb 100644 --- a/tests/gem5/dram-lowp/test_dram_lowp.py +++ b/tests/gem5/dram-lowp/test_dram_lowp.py @@ -34,7 +34,7 @@ verifiers=verifiers, config=joinpath(config.base_dir, "configs", "dram", "low_power_sweep.py"), config_args=["-p", "close_adaptive", "-r", "2"], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, ) @@ -44,6 +44,6 @@ verifiers=verifiers, config=joinpath(config.base_dir, "configs", "dram", "low_power_sweep.py"), config_args=["-p", "open_adaptive", "-r", "2"], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, ) diff --git a/tests/gem5/fs/linux/arm/test.py b/tests/gem5/fs/linux/arm/test.py index baccbd3..dff2e74 100644 --- a/tests/gem5/fs/linux/arm/test.py +++ b/tests/gem5/fs/linux/arm/test.py @@ -134,7 +134,7 @@ verifiers=verifier_list(name), # Add basic stat verifiers config=joinpath(filepath, "run.py"), config_args=args, - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, valid_hosts=valid_hosts, fixtures=(arm_fs_binaries,), @@ -152,7 +152,7 @@ verifiers=verifier_list(name), # TODO: Add basic stat verifiers config=joinpath(filepath, "run.py"), config_args=args, - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.long_tag, fixtures=(arm_fs_binaries,), uses_kvm=name in arm_fs_kvm_tests, diff --git a/tests/gem5/gem5-resources/test_download_resources.py b/tests/gem5/gem5-resources/test_download_resources.py index 55b57db..c0efc8b 100644 --- a/tests/gem5/gem5-resources/test_download_resources.py +++ b/tests/gem5/gem5-resources/test_download_resources.py @@ -41,6 +41,6 @@ config.base_dir, "tests", "gem5", "configs", "download_check.py" ), config_args=["--download-directory", resource_path], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.very_long_tag, ) diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index ddb41bb..ae814cb 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -45,7 +45,7 @@ config.base_dir, "configs", "example", "gem5_library", "arm-hello.py" ), config_args=[], - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.quick_tag, ) @@ -63,7 +63,7 @@ "riscv-hello-save-checkpoint.py", ), config_args=[], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.quick_tag, ) @@ -81,7 +81,7 @@ "riscv-hello-restore-checkpoint.py", ), config_args=[], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.quick_tag, ) @@ -101,7 +101,7 @@ "x86-ubuntu-run-with-kvm.py", ), config_args=[], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=(constants.host_x86_64_tag,), length=constants.long_tag, uses_kvm=True, @@ -119,7 +119,7 @@ "x86-ubuntu-run.py", ), config_args=[], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.long_tag, ) @@ -139,7 +139,7 @@ "x86-parsec-benchmarks.py", ), config_args=["--benchmark", "blackscholes", "--size", "simsmall"], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), protocol="MESI_Two_Level", valid_hosts=(constants.host_x86_64_tag,), length=constants.long_tag, @@ -168,7 +168,7 @@ "--ticks", "5000000000", ], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), protocol="MESI_Two_Level", valid_hosts=(constants.host_x86_64_tag,), length=constants.long_tag, @@ -190,7 +190,7 @@ "x86-gapbs-benchmarks.py", ), config_args=["--benchmark", "bfs", "--synthetic", "1", "--size", "1"], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), protocol="MESI_Two_Level", valid_hosts=(constants.host_x86_64_tag,), length=constants.long_tag, @@ -209,7 +209,7 @@ "riscv-ubuntu-run.py", ), config_args=[], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.long_tag, ) @@ -222,7 +222,7 @@ config.base_dir, "configs", "example", "lupv", "run_lupv.py" ), config_args=["timing", "1", "--max-ticks", "1000000000"], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.long_tag, ) @@ -239,7 +239,7 @@ "arm-ubuntu-boot-exit.py", ), config_args=[], - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=constants.long_tag, ) diff --git a/tests/gem5/gpu/test_gpu_ruby_random.py b/tests/gem5/gpu/test_gpu_ruby_random.py index b244f18..e29ecf2 100644 --- a/tests/gem5/gpu/test_gpu_ruby_random.py +++ b/tests/gem5/gpu/test_gpu_ruby_random.py @@ -53,7 +53,7 @@ config_args=["--test-length", "50000", "--num-dmas", "0"], valid_isas=(constants.vega_x86_tag,), valid_hosts=constants.supported_hosts, - length=constants.quick_tag, + length=constants.long_tag, ) diff --git a/tests/gem5/insttest_se/test.py b/tests/gem5/insttest_se/test.py index 9e9239e..4dde9d6 100644 --- a/tests/gem5/insttest_se/test.py +++ b/tests/gem5/insttest_se/test.py @@ -62,6 +62,6 @@ resource_path, "sparc", ], - valid_isas=(isa,), + valid_isas=(constants.all_compiled_tag,), length=constants.long_tag, ) diff --git a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py index 6dcb0c2..7467c02 100644 --- a/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py +++ b/tests/gem5/kvm-fork-tests/test_kvm_fork_run.py @@ -53,13 +53,13 @@ if mem_system == "mesi_two_level": protocol_to_use = None - isa_to_use = constants.x86_tag + isa_to_use = constants.all_compiled_tag elif mem_system == "mi_example": protocol_to_use = "MI_example" isa_to_use = constants.x86_tag else: protocol_to_use = None - isa_to_use = constants.vega_x86_tag + isa_to_use = constants.all_compiled_tag gem5_verify_config( name=name, diff --git a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py index 3f1ee9b..222c26b 100644 --- a/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py +++ b/tests/gem5/kvm-switch-tests/test_kvm_cpu_switch.py @@ -53,13 +53,13 @@ if mem_system == "mesi_two_level": protocol_to_use = None - isa_to_use = constants.x86_tag + isa_to_use = constants.all_compiled_tag elif mem_system == "mi_example": protocol_to_use = "MI_example" isa_to_use = constants.x86_tag else: protocol_to_use = None - isa_to_use = constants.vega_x86_tag + isa_to_use = constants.all_compiled_tag gem5_verify_config( name=name, diff --git a/tests/gem5/learning_gem5/part1_test.py b/tests/gem5/learning_gem5/part1_test.py index 5032fbe..5e44b0f 100644 --- a/tests/gem5/learning_gem5/part1_test.py +++ b/tests/gem5/learning_gem5/part1_test.py @@ -35,11 +35,25 @@ config=joinpath(config_path, "simple.py"), config_args=[], length=constants.quick_tag, - valid_isas=( - constants.vega_x86_tag, - constants.riscv_tag, - constants.arm_tag, - ), + valid_isas=(constants.all_compiled_tag,), +) + +gem5_verify_config( + name="simple_test_arm", + verifiers=(), + config=joinpath(config_path, "simple-arm.py"), + config_args=[], + length=constants.quick_tag, + valid_isas=(constants.all_compiled_tag,), +) + +gem5_verify_config( + name="simple_test_riscv", + verifiers=(), + config=joinpath(config_path, "simple-riscv.py"), + config_args=[], + length=constants.quick_tag, + valid_isas=(constants.all_compiled_tag,), ) # The "quick" two level tests. @@ -49,9 +63,5 @@ config=joinpath(config_path, "two_level.py"), config_args=[], length=constants.quick_tag, - valid_isas=( - constants.vega_x86_tag, - constants.riscv_tag, - constants.arm_tag, - ), + valid_isas=(constants.all_compiled_tag,), ) diff --git a/tests/gem5/learning_gem5/part2_test.py b/tests/gem5/learning_gem5/part2_test.py index 39792fb..916bdfd 100644 --- a/tests/gem5/learning_gem5/part2_test.py +++ b/tests/gem5/learning_gem5/part2_test.py @@ -35,7 +35,7 @@ verifiers=(get_verifier("simple"),), config=joinpath(config_path, "run_simple.py"), config_args=[], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), ) gem5_verify_config( @@ -43,7 +43,7 @@ verifiers=(get_verifier("hello_goodbye"),), config=joinpath(config_path, "hello_goodbye.py"), config_args=[], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), ) gem5_verify_config( @@ -52,7 +52,7 @@ config=joinpath(config_path, "simple_memobj.py"), config_args=[], # note: by default the above script uses x86 - valid_isas=(constants.vega_x86_tag,), + valid_isas=(constants.all_compiled_tag,), ) gem5_verify_config( @@ -61,7 +61,7 @@ config=joinpath(config_path, "simple_cache.py"), config_args=[], # note: by default the above script uses x86 - valid_isas=(constants.vega_x86_tag,), + valid_isas=(constants.all_compiled_tag,), ) # Note: for simple memobj and simple cache I want to use the traffic generator diff --git a/tests/gem5/learning_gem5/part3_test.py b/tests/gem5/learning_gem5/part3_test.py index d5a9d71..668f57d 100644 --- a/tests/gem5/learning_gem5/part3_test.py +++ b/tests/gem5/learning_gem5/part3_test.py @@ -40,9 +40,9 @@ config_args=[], protocol="MSI", # Currently only x86 has the threads test - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), # dynamically linked - valid_hosts=constants.target_host[constants.x86_tag], + valid_hosts=(constants.x86_tag,), length=constants.long_tag, ) @@ -53,6 +53,6 @@ config_args=[], protocol="MSI", # Currently only x86 has the threads test - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.long_tag, ) diff --git a/tests/gem5/m5_util/test_exit.py b/tests/gem5/m5_util/test_exit.py index e34e4ef..b79a8fad 100644 --- a/tests/gem5/m5_util/test_exit.py +++ b/tests/gem5/m5_util/test_exit.py @@ -66,5 +66,5 @@ resource_path, "x86", ], - valid_isas=(constants.vega_x86_tag,), + valid_isas=(constants.all_compiled_tag,), ) diff --git a/tests/gem5/m5threads_test_atomic/atomic_system.py b/tests/gem5/m5threads_test_atomic/atomic_system.py index 03c27a7..b7bd67d 100644 --- a/tests/gem5/m5threads_test_atomic/atomic_system.py +++ b/tests/gem5/m5threads_test_atomic/atomic_system.py @@ -50,11 +50,11 @@ if args.cpu_type == "DerivO3CPU": root.system.cpu = [ - DerivO3CPU(cpu_id=i) for i in range(int(args.num_cores)) + SparcDerivO3CPU(cpu_id=i) for i in range(int(args.num_cores)) ] elif args.cpu_type == "TimingSimpleCPU": root.system.cpu = [ - TimingSimpleCPU(cpu_id=i) for i in range(int(args.num_cores)) + SparcTimingSimpleCPU(cpu_id=i) for i in range(int(args.num_cores)) ] else: print("ERROR: CPU Type '" + args.cpu_type + "' not supported") diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py index c2cf846..d76463b 100644 --- a/tests/gem5/memory/test.py +++ b/tests/gem5/memory/test.py @@ -37,6 +37,7 @@ config=joinpath(getcwd(), "simple-run.py"), config_args=[], valid_isas=(constants.null_tag,), + length=constants.long_tag, ) simple_mem_params = [ @@ -57,6 +58,7 @@ config=joinpath(getcwd(), "simple-run.py"), config_args=args, valid_isas=(constants.null_tag,), + length=constants.long_tag, ) # This tests for validity as well as performance gem5_verify_config( @@ -65,6 +67,7 @@ config=joinpath(getcwd(), "memtest-run.py"), config_args=[], valid_isas=(constants.null_tag,), + length=constants.long_tag, ) null_tests = [ @@ -132,4 +135,5 @@ config_args=args, valid_isas=(constants.null_tag,), valid_hosts=constants.supported_hosts, + length=constants.long_tag, ) diff --git a/tests/gem5/multi_isa/test_multi_isa.py b/tests/gem5/multi_isa/test_multi_isa.py index 4d7a18c..2c6a96c 100644 --- a/tests/gem5/multi_isa/test_multi_isa.py +++ b/tests/gem5/multi_isa/test_multi_isa.py @@ -36,15 +36,6 @@ "riscv": constants.riscv_tag, } -length_map = { - "sparc": constants.long_tag, - "mips": constants.long_tag, - "null": constants.quick_tag, - "arm": constants.quick_tag, - "x86": constants.quick_tag, - "power": constants.long_tag, - "riscv": constants.long_tag, -} for isa in isa_map.keys(): gem5_verify_config( @@ -57,7 +48,7 @@ config_args=["-e", isa], valid_isas=(isa_map[isa],), valid_hosts=constants.supported_hosts, - length=length_map[isa], + length=constants.long_tag, ) gem5_verify_config( @@ -74,7 +65,7 @@ config_args=["-e", isa], valid_isas=(isa_map[isa],), valid_hosts=constants.supported_hosts, - length=length_map[isa], + length=constants.long_tag, ) if isa != "null": @@ -94,5 +85,5 @@ config_args=["-e", isa], valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, - length=constants.long_tag, + length=constants.quick_tag, ) diff --git a/tests/gem5/parsec-benchmarks/test_parsec.py b/tests/gem5/parsec-benchmarks/test_parsec.py index 86cfa7c..11735ab 100644 --- a/tests/gem5/parsec-benchmarks/test_parsec.py +++ b/tests/gem5/parsec-benchmarks/test_parsec.py @@ -75,7 +75,7 @@ "--resource-directory", resource_path, ], - valid_isas=(constants.x86_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=(constants.host_x86_64_tag,), length=length, uses_kvm=True, diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py b/tests/gem5/riscv-boot-tests/test_linux_boot.py index 5ac7bec..5ba4fa5 100644 --- a/tests/gem5/riscv-boot-tests/test_linux_boot.py +++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py @@ -86,7 +86,7 @@ "riscv_boot_exit_run.py", ), config_args=config_args, - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, length=length, ) @@ -133,7 +133,7 @@ test_boot( cpu="minor", num_cpus=1, - cache_type="mi_example", + cache_type="mesi_two_level", memory_class="SingleChannelDDR3_2133", length=constants.quick_tag, to_tick=10000000000, @@ -142,7 +142,7 @@ test_boot( cpu="minor", num_cpus=8, - cache_type="mi_example", + cache_type="mesi_two_level", memory_class="SingleChannelDDR3_2133", length=constants.quick_tag, to_tick=10000000000, @@ -152,7 +152,7 @@ test_boot( cpu="timing", num_cpus=1, - cache_type="mi_example", + cache_type="mesi_two_level", memory_class="SingleChannelDDR4_2400", length=constants.quick_tag, to_tick=10000000000, @@ -179,7 +179,7 @@ test_boot( cpu="timing", num_cpus=4, - cache_type="mi_example", + cache_type="mesi_two_level", memory_class="DualChannelDDR4_2400", length=constants.quick_tag, to_tick=10000000000, @@ -202,7 +202,7 @@ # test_boot( # cpu="timing", # num_cpus=1, -# cache_type="mi_example", +# cache_type="mesi_two_level", # memory_class="SingleChannelLPDDR3_1600", # length=constants.long_tag, # ) @@ -210,7 +210,7 @@ # test_boot( # cpu="timing", # num_cpus=4, -# cache_type="mi_example", +# cache_type="mesi_two_level", # memory_class="DualChannelDDR4_2400", # length=constants.long_tag, # ) @@ -226,7 +226,7 @@ # test_boot( # cpu="o3", # num_cpus=8, -# cache_type="mi_example", +# cache_type="mesi_two_level", # memory_class="HBM2Stack", # length=constants.long_tag, # ) diff --git a/tests/gem5/se_mode/hello_se/test_hello_se.py b/tests/gem5/se_mode/hello_se/test_hello_se.py index a9dea82..1aaac4a 100644 --- a/tests/gem5/se_mode/hello_se/test_hello_se.py +++ b/tests/gem5/se_mode/hello_se/test_hello_se.py @@ -79,17 +79,6 @@ constants.sparc_tag: ("timing", "atomic"), } -# We only want to test x86, arm, and riscv on quick. Mips and sparc will be -# left for long. -os_length = { - constants.vega_x86_tag: constants.quick_tag, - constants.arm_tag: constants.quick_tag, - constants.mips_tag: constants.long_tag, - constants.riscv_tag: constants.quick_tag, - constants.sparc_tag: constants.long_tag, -} - - if config.bin_path: resource_path = config.bin_path else: @@ -117,9 +106,9 @@ isa_str_map[isa], ] + input, - valid_isas=(isa,), + valid_isas=(constants.all_compiled_tag,), valid_hosts=hosts, - length=os_length[isa], + length=constants.quick_tag, ) diff --git a/tests/gem5/se_mode/hello_se/test_se_multicore.py b/tests/gem5/se_mode/hello_se/test_se_multicore.py index cee84a6..55fc61f 100644 --- a/tests/gem5/se_mode/hello_se/test_se_multicore.py +++ b/tests/gem5/se_mode/hello_se/test_se_multicore.py @@ -51,6 +51,6 @@ "--resource-directory", resource_path, ], - valid_isas=(constants.vega_x86_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, ) diff --git a/tests/gem5/stats/test_hdf5.py b/tests/gem5/stats/test_hdf5.py index 187e1e8..993534a 100644 --- a/tests/gem5/stats/test_hdf5.py +++ b/tests/gem5/stats/test_hdf5.py @@ -94,5 +94,5 @@ "arm", ], gem5_args=["--stats-file=h5://stats.h5"], - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), ) diff --git a/tests/gem5/stdlib/test_base_cpu_processor.py b/tests/gem5/stdlib/test_base_cpu_processor.py index d6b0561..cbc6767 100644 --- a/tests/gem5/stdlib/test_base_cpu_processor.py +++ b/tests/gem5/stdlib/test_base_cpu_processor.py @@ -40,7 +40,7 @@ config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py" ), config_args=["x86-hello64-static", "timing", "x86", "-b"], - valid_isas=(constants.vega_x86_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, ) @@ -52,7 +52,7 @@ config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py" ), config_args=["riscv-hello", "atomic", "riscv", "-b"], - valid_isas=(constants.riscv_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, ) @@ -64,6 +64,6 @@ config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py" ), config_args=["arm-hello64-static", "o3", "arm", "-b"], - valid_isas=(constants.arm_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, ) diff --git a/tests/gem5/stdlib/test_requires.py b/tests/gem5/stdlib/test_requires.py index 7d3282c..a70ca6b 100644 --- a/tests/gem5/stdlib/test_requires.py +++ b/tests/gem5/stdlib/test_requires.py @@ -39,9 +39,9 @@ length_map = { "sparc": constants.long_tag, "mips": constants.long_tag, - "null": constants.quick_tag, - "arm": constants.quick_tag, - "x86": constants.quick_tag, + "null": constants.long_tag, + "arm": constants.long_tag, + "x86": constants.long_tag, "power": constants.long_tag, "riscv": constants.long_tag, } diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py b/tests/gem5/traffic_gen/test_memory_traffic_gen.py index 75d21dc..10e2bd2 100644 --- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py +++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py @@ -42,18 +42,6 @@ memory: str, *args, ) -> None: - protocol_map = { - "NoCache": None, - "PrivateL1": None, - "PrivateL1PrivateL2": None, - "MESITwoLevel": "MESI_Two_Level", - } - tag_map = { - "NoCache": constants.quick_tag, - "PrivateL1": constants.quick_tag, - "PrivateL1PrivateL2": constants.quick_tag, - "MESITwoLevel": constants.long_tag, - } name = ( "test-memory-" @@ -75,10 +63,9 @@ ), config_args=[generator, generator_cores, cache, module, memory] + list(args), - valid_isas=(constants.null_tag,), - protocol=protocol_map[cache], + valid_isas=(constants.all_compiled_tag,), valid_hosts=constants.supported_hosts, - length=tag_map[cache], + length=constants.quick_tag, ) diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py b/tests/gem5/x86-boot-tests/test_linux_boot.py index be8010d..ecda2ff 100644 --- a/tests/gem5/x86-boot-tests/test_linux_boot.py +++ b/tests/gem5/x86-boot-tests/test_linux_boot.py @@ -64,13 +64,13 @@ if mem_system == "mesi_two_level": protocol_to_use = None - isa_to_use = constants.x86_tag + isa_to_use = constants.all_compiled_tag elif mem_system == "mi_example": protocol_to_use = "MI_example" isa_to_use = constants.x86_tag else: protocol_to_use = None - isa_to_use = constants.vega_x86_tag + isa_to_use = constants.all_compiled_tag gem5_verify_config( name=name, diff --git a/tests/pyunit/test_run.py b/tests/pyunit/test_run.py index 0fc8e6c..76cd5f7 100644 --- a/tests/pyunit/test_run.py +++ b/tests/pyunit/test_run.py @@ -43,6 +43,6 @@ config=os.path.join(os.getcwd(), os.pardir, "run_pyunit.py"), verifiers=(), config_args=[], - valid_isas=(constants.null_tag,), + valid_isas=(constants.all_compiled_tag,), length=constants.quick_tag, ) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/63374?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I533689ad6848233867bdba9e9a43bb5840ed65c7 Gerrit-Change-Number: 63374 Gerrit-PatchSet: 15 Gerrit-Owner: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Bobby Bruce <bbruce@ucdavis.edu> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-CC: Jason Lowe-Power <power.jg@gmail.com> Gerrit-MessageType: merged