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Simulate accelerator-like NoC structure in gem5

VK
VANI KRISHNA BARLA
Tue, Mar 19, 2024 4:18 AM

I've limited exposure to gem5 functioning with respect to communication in the NoC (NetworkUnit/InputUnit/Routers) at packet level.

My primary objective is to investigate the ramifications of employing an alternate number representation system (POSIT) in contrast to the IEEE 754 floating-point standard. Specifically, while simulating I need to analyse the reduced bit width impact in terms of storage in memory and usage of the system bus between the memory unit and the nodes, and if possible study the impact of an alternate MAC unit which operates for different bit widths with lower power and area requirements.

Could anyone kindly provide some starting point or insights on customizing such simulations within gem5? Any help would be greatly appreciated. Thank you in advance for your assistance. Regards,

Vani

I've limited exposure to gem5 functioning with respect to communication in the NoC (NetworkUnit/InputUnit/Routers) at packet level. My primary objective is to investigate the ramifications of employing an alternate number representation system (POSIT) in contrast to the IEEE 754 floating-point standard. Specifically, while simulating I need to analyse the reduced bit width impact in terms of storage in memory and usage of the system bus between the memory unit and the nodes, and if possible study the impact of an alternate MAC unit which operates for different bit widths with lower power and area requirements. Could anyone kindly provide some starting point or insights on customizing such simulations within gem5? Any help would be greatly appreciated. Thank you in advance for your assistance. Regards, Vani