uint64_t addr = addresses[i];

            uint8_t share = shares[i];

            // Create a new packet for the share

            // Using the Packet constructor with the appropriate

            Request::Flags flags;

            flags.set(Request::UNCACHEABLE);

            flags.set(Request::PHYSICAL);

            flags.set(0x00002000|0x00001000);

            RequestPtr req = std::make_shared<Request>(addr, 1, flags, 0

            PacketPtr new_pkt = new Packet(req, pkt->cmd);


            // Allocate data for the new packet and copy the share data

            new_pkt->allocate();

            memcpy(new_pkt->getPtr<uint8_t>(), &share, sizeof(share));


            addToWriteQueue(new_pkt, pkt_count, dram);

Dear gem5 community, I am working on simulating a modified memory system in gem5 where I intend to introduce additional read and write operations within the memory controller. To elaborate, for every incoming read or write request to the memory controller, I wish to trigger further reads and writes based on the address of the original request. In the recvTimingReq function of mem_ctrl.cc, I've added the following changes: uint64_t addr = addresses[i]; uint8_t share = shares[i]; // Create a new packet for the share // Using the Packet constructor with the appropriate parameters Request::Flags flags; flags.set(Request::UNCACHEABLE); flags.set(Request::PHYSICAL); flags.set(0x00002000|0x00001000); RequestPtr req = std::make_shared<Request>(addr, 1, flags, 0 ); PacketPtr new_pkt = new Packet(req, pkt->cmd); // Allocate data for the new packet and copy the share data new_pkt->allocate(); memcpy(new_pkt->getPtr<uint8_t>(), &share, sizeof(share)); addToWriteQueue(new_pkt, pkt_count, dram); Here, I am trying to generate a new request with addr as the destination address and share as the data. However, upon running the simulation, I encounter the following error: [image: image.png] From the error, it appears that the new requests I'm generating aren't present in the routeTo map of the coherent crossbar. My questions are: How can I correctly add my new requests to the routeTo map from within the memory controller? Is there an issue with how I'm defining or initializing these new requests in memory controller? Any guidance or suggestions would be immensely appreciated. Thank you for your time and support. Best regards, Haoran -- PhD in Computer Science and Engineering University of Notre Dame Department of Computer Science and Engineering a:222 Cushing Hall, Notre Dame, IN, 46556,USA m: (847) 987 0031