What happens when a atomic only port is accessed in Timing simulation?
Hi All,
I am building a simulated system with a control registers port that only implemented recvAtomic function. The control port is connected to the IOBridge, and the system is running in timing mode. There is no problem to access the registers from CPU, but I wonder what the system does with the delay? I believe the atomic port would be treated as a timing port that has no delays. But is the delay of IOBridge and other system buses counted?
Thanks,
Zehan
Hi Zehan,
Atomic memory accesses should not be used during the same simulation loop
as timing accesses. I.e., you should not call "sendAtomic" on a port during
the same simulation loop that you call "sendTiming". If there isn't a panic
in that case, there probably should be.
If you want to get a value out of memory in 0 time (e.g., for debugging or
to model a "perfect" hardware component) you can use functional accesses
during the timing simulation. You can also exit the simulation loop and
switch between timing and atomic modes.
Cheers,
Jason
On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao z99gao@uwaterloo.ca wrote:
Hi All,
I am building a simulated system with a control registers
port that only implemented recvAtomic function. The control port is
connected to the IOBridge, and the system is running in timing mode. There
is no problem to access the registers from CPU, but I wonder what the
system does with the delay? I believe the atomic port would be treated as a
timing port that has no delays. But is the delay of IOBridge and other
system buses counted?
Thanks,
Zehan
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Thanks for your advice. My guess is that it's the ports connected to the atomic-only port converts a timing request to atomic, and calls the recvAtomic function. In this case it's the XBar. I will try to measure how it's delayed.
From: Jason Lowe-Power jason@lowepower.com
Sent: Wednesday, July 6, 2022, 11:09 a.m.
To: The gem5 Users mailing list gem5-users@gem5.org
Subject: [gem5-users] Re: What happens when a atomic only port is accessed in Timing simulation?
Hi Zehan,
Atomic memory accesses should not be used during the same simulation loop as timing accesses. I.e., you should not call "sendAtomic" on a port during the same simulation loop that you call "sendTiming". If there isn't a panic in that case, there probably should be.
If you want to get a value out of memory in 0 time (e.g., for debugging or to model a "perfect" hardware component) you can use functional accesses during the timing simulation. You can also exit the simulation loop and switch between timing and atomic modes.
Cheers,
Jason
On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao <z99gao@uwaterloo.camailto:z99gao@uwaterloo.ca> wrote:
Hi All,
I am building a simulated system with a control registers port that only implemented recvAtomic function. The control port is connected to the IOBridge, and the system is running in timing mode. There is no problem to access the registers from CPU, but I wonder what the system does with the delay? I believe the atomic port would be treated as a timing port that has no delays. But is the delay of IOBridge and other system buses counted?
Thanks,
Zehan
gem5-users mailing list -- gem5-users@gem5.orgmailto:gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.orgmailto:gem5-users-leave@gem5.org
Hi Zehan,
I wouldn't say it converts the timing request to atomic. Instead, I would
say that for the functional access (sorry for the overloaded term here...
I mean functional as in the place it does the "execution" part of the
model) it uses the same C++ function for both timing and atomic. The timing
should be handled in the delay when the sendTimingReq or sendTimingResp
events are scheduled.
Cheers,
Jason
On Wed, Jul 6, 2022 at 8:21 AM Zehan Gao z99gao@uwaterloo.ca wrote:
Thanks for your advice. My guess is that it's the ports connected to the
atomic-only port converts a timing request to atomic, and calls the
recvAtomic function. In this case it's the XBar. I will try to measure how
it's delayed.
From: Jason Lowe-Power jason@lowepower.com
Sent: Wednesday, July 6, 2022, 11:09 a.m.
To: The gem5 Users mailing list gem5-users@gem5.org
Subject: [gem5-users] Re: What happens when a atomic only port is
accessed in Timing simulation?
Hi Zehan,
Atomic memory accesses should not be used during the same simulation loop
as timing accesses. I.e., you should not call "sendAtomic" on a port during
the same simulation loop that you call "sendTiming". If there isn't a panic
in that case, there probably should be.
If you want to get a value out of memory in 0 time (e.g., for debugging or
to model a "perfect" hardware component) you can use functional accesses
during the timing simulation. You can also exit the simulation loop and
switch between timing and atomic modes.
Cheers,
Jason
On Tue, Jul 5, 2022 at 9:56 PM Zehan Gao z99gao@uwaterloo.ca wrote:
Hi All,
I am building a simulated system with a control registers
port that only implemented recvAtomic function. The control port is
connected to the IOBridge, and the system is running in timing mode. There
is no problem to access the registers from CPU, but I wonder what the
system does with the delay? I believe the atomic port would be treated as a
timing port that has no delays. But is the delay of IOBridge and other
system buses counted?
Thanks,
Zehan
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.org
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.org