Hi all, I'm using the O3CPU model for performance evaluation, we have two LoadUnit, I find that if dual load issued same time, the second load will be blocked and rescheduled after a few cycles of latency. The O3CPUAll and Xbar trace show: *The crossbar layer is now busy from tick xxx to xxx* *....* *Memory requst from inst was not sent( cache is blocked: 1, cache_got_blocked: 1)* My question is: How to modify the model to support dual load/store with the XBar?

On 2/20/2024 8:18 AM, chengyong zhong via gem5-users wrote: > Hi all, > I'm using the O3CPU model for performance evaluation, we have two LoadUnit, I find that if dual load issued same time, > the second load will be blocked and rescheduled after a few cycles of latency. > The O3CPUAll and Xbar trace show: > /The crossbar layer is now busy from tick xxx to xxx/ > /..../ > /Memory requst from inst was not sent( cache is blocked: 1, cache_got_blocked: 1)/ > My question is: How to modify the model to support dual load/store with the XBar? If there is only one bus to the cache, as there seems to be, you need to add an additional path to the cache and rework the cache to support dual access. As we computer scientists say "this is a mere matter of programming", but IMO it is not trivial. Unless I've missed something, gem5 does not provide dual / multi port caches at present. Regards - EM