gem5&&instruction execute&&ALU
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is this instruction executed?
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is
this instruction executed?
gem5 does not model at the circuit level. A piece of C++ code,
defined with the instruction, will perform the operation. It
charges an indicated amount of time, according to the functional
unit. gem5 deals with all the queueing and timing, but does not
model at the gate level.
Best wishes - EM
On 4/20/2023 11:33 AM, Eliot Moss via gem5-users wrote:
On 4/20/2023 10:58 AM, 中国石油大学张天 via gem5-users wrote:
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5,
shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how
is this instruction executed?
gem5 does not model at the circuit level. A piece of C++ code,
defined with the instruction, will perform the operation. It
charges an indicated amount of time, according to the functional
unit. gem5 deals with all the queueing and timing, but does not
model at the gate level.
Best wishes - EM
It occurred to me to add a little bit to this. The out-of-order (O3)
cpu model allows you define a bunch of different functional units,
which ones can handle which instructions, how many of each the cpu
has, their timing, etc. For that model anyway there is no single
"ALU". What I said above still holds: gem5 defines enough to be
able to determine timing (and an estimate of power consumption) but
it does not model at a more detailed level than that.
The model of DRAM chips is somewhat more detailed and realistic
(perhaps), but that's necessary to get obtain accurate timing
predictions.
HTH -- EM
Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in Gem5. I'm not sure if it's feasible. I am so obsessed with ALU because I need to provide a rough reproduction of an article that uses the Residual Number System (RNS) to design a CPU core. Since I first learned about Gem5, I wanted to keep working on this tool. But now it doesn't seem very good.
------------------ 原始邮件 ------------------
发件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
发送时间: 2023年4月20日(星期四) 晚上10:58
收件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
抄送: "中国石油大学张天"<upczhangtian@qq.com>;
主题: [gem5-users] gem5&&instruction execute&&ALU
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is this instruction executed?
On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote:
Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to
design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in
Gem5. I'm not sure if it's feasible. I am so obsessed with ALU because I need to provide a rough
reproduction of an article that uses the Residual Number System (RNS) to design a CPU core. Since I
first learned about Gem5, I wanted to keep working on this tool. But now it doesn't seem very good.
As far as gem5 is concerned, you could just write the
operations in C++. Though if the overall result is the
same as regular binary arithmetic, there is little point.
gem5 simply does not model at that level. What would you
be showing?
If you want to be modeling things at that level, maybe
building up a CPU using an FPGA board is for you.
Best wishes - EM
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I send you an email, you always reject it.
------------------ 原始邮件 ------------------
发件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
发送时间: 2023年4月21日(星期五) 凌晨0:10
收件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
抄送: "中国石油大学张天"<upczhangtian@qq.com>; "Eliot Moss"<moss@cs.umass.edu>;
主题: [gem5-users] Re: 回复：gem5&&instruction execute&&ALU
On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote:
> Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to
> design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in
> Gem5. I'm not sure if it's feasible. I am so obsessed with ALU because I need to provide a rough
> reproduction of an article that uses the Residual Number System (RNS) to design a CPU core. Since I
> first learned about Gem5, I wanted to keep working on this tool. But now it doesn't seem very good.
As far as gem5 is concerned, you could just write the
operations in C++. Though if the overall result is the
same as regular binary arithmetic, there is little point.
gem5 simply does not model at that level. What would you
be showing?
If you want to be modeling things at that level, maybe
building up a CPU using an FPGA board is for you.
Best wishes - EM
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.org
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I send you an email, you always reject it.
------------------ 原始邮件 ------------------
发件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
发送时间: 2023年4月21日(星期五) 凌晨0:10
收件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
抄送: "中国石油大学张天"<upczhangtian@qq.com>; "Eliot Moss"<moss@cs.umass.edu>;
主题: [gem5-users] Re: 回复：gem5&&instruction execute&&ALU
On 4/20/2023 11:56 AM, 中国石油大学张天 via gem5-users wrote:
> Thank you for your reply again, hahahaha. I have been thinking recently whether it is possible to
> design ALU through Verilog, translate it through Verilator or other tools, and ultimately use it in
> Gem5. I'm not sure if it's feasible. I am so obsessed with ALU because I need to provide a rough
> reproduction of an article that uses the Residual Number System (RNS) to design a CPU core. Since I
> first learned about Gem5, I wanted to keep working on this tool. But now it doesn't seem very good.
As far as gem5 is concerned, you could just write the
operations in C++. Though if the overall result is the
same as regular binary arithmetic, there is little point.
gem5 simply does not model at that level. What would you
be showing?
If you want to be modeling things at that level, maybe
building up a CPU using an FPGA board is for you.
Best wishes - EM
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.org
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I send you an email, you always reject it.
------------------ 原始邮件 ------------------
发件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
发送时间: 2023年4月20日(星期四) 晚上10:58
收件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
抄送: "中国石油大学张天"<upczhangtian@qq.com>;
主题: [gem5-users] gem5&&instruction execute&&ALU
Hello everyone, I would like to ask, when executing non memory access instructions in Gem5, shouldn't it be executed in ALU? But ALU has not been specifically designed and implemented, how is this instruction executed?
On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote:
Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already
midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I
send you an email, you always reject it.
If you mean I am always saying "that's not a concept in gem5",
then I am just trying to be honest. There's nothing wrong with
playing around with a residual based ALU. I just don't see how
it makes any sense in gem5 because of the level at which it
models things. You might be able to connect such a hardware
model up, invoke it whenever an instruction comes along that
wants to use it, and plug the result back in, but what would
that really accomplish, assuming it is just an alternative
implementation (at the gate level) of existing instructions?
They aren't modeled at the gate level anyway. Maybe it would
stress test your model, but assuming the mode is correct, I
suspect all it would do is dramatically slow down the simulation.
May be I/we could be more helpful if you could clarify your
broader goal, what you're trying to accomplish, and why you
think gem5 is a good vehicle for it. If I am just totally
misunderstanding, I apologize.
Regards - EM
Sorry for taking so long to reply to you. The goal I want to achieve is a simple reproduction of this article (Extending Moore's Law via Computationally Error Tolrant Computing), ultimately completing such a system. I believe the core goal should be the design of the RRNS core. Because it did mention gem5, I thought I could use gem5 as a tool or other tools such as McPAT to achieve this. But through my understanding of the ALU part of Gem5, I found that there was no specific implementation, so I thought about using a translator to implement it through Gem5+RTL. The attachment contains a paper that guided me to generate these ideas, which you can read.
I am currently quite confused, and I hope you can provide me with some suggestions after fully understanding.
Thank you.
------------------ 原始邮件 ------------------
发件人: "moss" <gem5-users@gem5.org>;
发送时间: 2023年4月21日(星期五) 凌晨0:34
收件人: "The gem5 Users mailing list"<gem5-users@gem5.org>;
抄送: "中国石油大学张天"<upczhangtian@qq.com>;"Eliot Moss"<moss@cs.umass.edu>;
主题: [gem5-users] Re: 回复：Re: 回复：gem5&&instruction execute&&ALU
On 4/20/2023 12:20 PM, 中国石油大学张天 via gem5-users wrote:
> Okay, thank you. I have received your suggestion and I will think it over tomorrow. It's already
> midnight here, so I'll go to bed first 😊。 Thank you again. By the way, it seems that every time I
> send you an email, you always reject it.
If you mean I am always saying "that's not a concept in gem5",
then I am just trying to be honest. There's nothing wrong with
playing around with a residual based ALU. I just don't see how
it makes any sense in gem5 because of the level at which it
models things. You might be able to connect such a hardware
model up, invoke it whenever an instruction comes along that
wants to use it, and plug the result back in, but what would
that really accomplish, assuming it is just an alternative
implementation (at the gate level) of existing instructions?
They aren't modeled at the gate level anyway. Maybe it would
stress test your model, but assuming the mode is correct, I
suspect all it would do is dramatically slow down the simulation.
May be I/we could be more helpful if you could clarify your
broader goal, what you're trying to accomplish, and why you
think gem5 is a good vehicle for it. If I am just totally
misunderstanding, I apologize.
Regards - EM
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-leave@gem5.org