// First loop through the integer registers.
  for (int i = 0; i < regClasses.at(IntRegClass).numRegs(); ++i) {

  // Then loop through the floating point registers.
  for (int i = 0; i < regClasses.at(FloatRegClass).numRegs(); ++i) {

  // loop through the Condition Code registers.
  for (int i = 0; i < regClasses.at(CCRegClass).numRegs(); ++i) {

  virtual void setRegFlat(const RegId &reg, RegVal val);
  virtual void setRegFlat(const RegId &reg, const void *val) = 0;

Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/49778 ) ( 74 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu: Stop using or providing legacy (read|set)Reg* accessors. ...................................................................... cpu: Stop using or providing legacy (read|set)Reg* accessors. These have now all been replaced with (get|set)Reg* accessors throughout the code base. Change-Id: I7d16d697ecfb813eb870068677f77636d41af28b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49778 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/cpu/thread_context.cc M src/cpu/thread_context.hh 2 files changed, 34 insertions(+), 144 deletions(-) Approvals: Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 400bc16..8f0fafb 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -66,8 +66,9 @@ // First loop through the integer registers. for (int i = 0; i < regClasses.at(IntRegClass).numRegs(); ++i) { - RegVal t1 = one->readIntReg(i); - RegVal t2 = two->readIntReg(i); + RegId reg(IntRegClass, i); + RegVal t1 = one->getReg(reg); + RegVal t2 = two->getReg(reg); if (t1 != t2) panic("Int reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -75,8 +76,9 @@ // Then loop through the floating point registers. for (int i = 0; i < regClasses.at(FloatRegClass).numRegs(); ++i) { - RegVal t1 = one->readFloatReg(i); - RegVal t2 = two->readFloatReg(i); + RegId reg(FloatRegClass, i); + RegVal t1 = one->getReg(reg); + RegVal t2 = two->getReg(reg); if (t1 != t2) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -124,8 +126,9 @@ // loop through the Condition Code registers. for (int i = 0; i < regClasses.at(CCRegClass).numRegs(); ++i) { - RegVal t1 = one->readCCReg(i); - RegVal t2 = two->readCCReg(i); + RegId reg(CCRegClass, i); + RegVal t1 = one->getReg(reg); + RegVal t2 = two->getReg(reg); if (t1 != t2) panic("CC reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); @@ -222,7 +225,7 @@ const size_t numFloats = regClasses.at(FloatRegClass).numRegs(); RegVal floatRegs[numFloats]; for (int i = 0; i < numFloats; ++i) - floatRegs[i] = tc.readFloatRegFlat(i); + floatRegs[i] = tc.getRegFlat(RegId(FloatRegClass, i)); // This is a bit ugly, but needed to maintain backwards // compatibility. arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats); @@ -230,7 +233,8 @@ const size_t numVecs = regClasses.at(VecRegClass).numRegs(); std::vector<TheISA::VecRegContainer> vecRegs(numVecs); for (int i = 0; i < numVecs; ++i) { - vecRegs[i] = tc.readVecRegFlat(i); + RegId reg(VecRegClass, i); + tc.getRegFlat(RegId(VecRegClass, i), &vecRegs[i]); } SERIALIZE_CONTAINER(vecRegs); @@ -244,14 +248,14 @@ const size_t numInts = regClasses.at(IntRegClass).numRegs(); RegVal intRegs[numInts]; for (int i = 0; i < numInts; ++i) - intRegs[i] = tc.readIntRegFlat(i); + intRegs[i] = tc.getRegFlat(RegId(IntRegClass, i)); SERIALIZE_ARRAY(intRegs, numInts); const size_t numCcs = regClasses.at(CCRegClass).numRegs(); if (numCcs) { RegVal ccRegs[numCcs]; for (int i = 0; i < numCcs; ++i) - ccRegs[i] = tc.readCCRegFlat(i); + ccRegs[i] = tc.getRegFlat(RegId(CCRegClass, i)); SERIALIZE_ARRAY(ccRegs, numCcs); } @@ -271,13 +275,13 @@ // compatibility. arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats); for (int i = 0; i < numFloats; ++i) - tc.setFloatRegFlat(i, floatRegs[i]); + tc.setRegFlat(RegId(FloatRegClass, i), floatRegs[i]); const size_t numVecs = regClasses.at(VecRegClass).numRegs(); std::vector<TheISA::VecRegContainer> vecRegs(numVecs); UNSERIALIZE_CONTAINER(vecRegs); for (int i = 0; i < numVecs; ++i) { - tc.setVecRegFlat(i, vecRegs[i]); + tc.setRegFlat(RegId(VecRegClass, i), &vecRegs[i]); } const size_t numPreds = regClasses.at(VecPredRegClass).numRegs(); @@ -291,14 +295,14 @@ RegVal intRegs[numInts]; UNSERIALIZE_ARRAY(intRegs, numInts); for (int i = 0; i < numInts; ++i) - tc.setIntRegFlat(i, intRegs[i]); + tc.setRegFlat(RegId(IntRegClass, i), intRegs[i]); const size_t numCcs = regClasses.at(CCRegClass).numRegs(); if (numCcs) { RegVal ccRegs[numCcs]; UNSERIALIZE_ARRAY(ccRegs, numCcs); for (int i = 0; i < numCcs; ++i) - tc.setCCRegFlat(i, ccRegs[i]); + tc.setRegFlat(RegId(CCRegClass, i), ccRegs[i]); } std::unique_ptr<PCStateBase> pc_state(tc.pcState().clone()); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 835ac46..3874ec1 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -200,73 +200,6 @@ virtual void setReg(const RegId &reg, RegVal val); virtual void setReg(const RegId &reg, const void *val); - RegVal - readIntReg(RegIndex reg_idx) const - { - return getReg(RegId(IntRegClass, reg_idx)); - } - - RegVal - readFloatReg(RegIndex reg_idx) const - { - return getReg(RegId(FloatRegClass, reg_idx)); - } - - TheISA::VecRegContainer - readVecReg(const RegId &reg) const - { - TheISA::VecRegContainer val; - getReg(reg, &val); - return val; - } - TheISA::VecRegContainer& - getWritableVecReg(const RegId& reg) - { - return *(TheISA::VecRegContainer *)getWritableReg(reg); - } - - RegVal - readVecElem(const RegId& reg) const - { - return getReg(reg); - } - - RegVal - readCCReg(RegIndex reg_idx) const - { - return getReg(RegId(CCRegClass, reg_idx)); - } - - void - setIntReg(RegIndex reg_idx, RegVal val) - { - setReg(RegId(IntRegClass, reg_idx), val); - } - - void - setFloatReg(RegIndex reg_idx, RegVal val) - { - setReg(RegId(FloatRegClass, reg_idx), val); - } - - void - setVecReg(const RegId& reg, const TheISA::VecRegContainer &val) - { - setReg(reg, &val); - } - - void - setVecElem(const RegId& reg, RegVal val) - { - setReg(reg, val); - } - - void - setCCReg(RegIndex reg_idx, RegVal val) - { - setReg(RegId(CCRegClass, reg_idx), val); - } - virtual const PCStateBase &pcState() const = 0; virtual void pcState(const PCStateBase &val) = 0; @@ -321,69 +254,6 @@ virtual void setRegFlat(const RegId &reg, RegVal val); virtual void setRegFlat(const RegId &reg, const void *val) = 0; - - RegVal - readIntRegFlat(RegIndex idx) const - { - return getRegFlat(RegId(IntRegClass, idx)); - } - void - setIntRegFlat(RegIndex idx, RegVal val) - { - setRegFlat(RegId(IntRegClass, idx), val); - } - - RegVal - readFloatRegFlat(RegIndex idx) const - { - return getRegFlat(RegId(FloatRegClass, idx)); - } - void - setFloatRegFlat(RegIndex idx, RegVal val) - { - setRegFlat(RegId(FloatRegClass, idx), val); - } - - TheISA::VecRegContainer - readVecRegFlat(RegIndex idx) const - { - TheISA::VecRegContainer val; - getRegFlat(RegId(VecRegClass, idx), &val); - return val; - } - TheISA::VecRegContainer& - getWritableVecRegFlat(RegIndex idx) - { - return *(TheISA::VecRegContainer *) - getWritableRegFlat(RegId(VecRegClass, idx)); - } - void - setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer& val) - { - setRegFlat(RegId(VecRegClass, idx), &val); - } - - RegVal - readVecElemFlat(RegIndex idx) const - { - return getRegFlat(RegId(VecElemClass, idx)); - } - void - setVecElemFlat(RegIndex idx, RegVal val) - { - setRegFlat(RegId(VecElemClass, idx), val); - } - - RegVal - readCCRegFlat(RegIndex idx) const - { - return getRegFlat(RegId(CCRegClass, idx)); - } - void - setCCRegFlat(RegIndex idx, RegVal val) - { - setRegFlat(RegId(CCRegClass, idx), val); - } /** @} */ // hardware transactional memory -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49778 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7d16d697ecfb813eb870068677f77636d41af28b Gerrit-Change-Number: 49778 Gerrit-PatchSet: 77 Gerrit-Owner: Gabe Black <gabe.black@gmail.com> Gerrit-Reviewer: Gabe Black <gabe.black@gmail.com> Gerrit-Reviewer: Giacomo Travaglini <giacomo.travaglini@arm.com> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-MessageType: merged