To whom it may concern:

I would like to delve into the gem5’s working paradigm, especially getting the lowdown on how it is executed in a serial discrete event simulation (DES) manner on the CPU, as described in its introduction. I am wondering if there is any material discussing this topic.

Yee Hin, Chong
CRAFT Lab, Tsinghua University, China.

Hi,

DES is a very well documented topic. You can find a lot of resources about this topic searching for “discrete event simulation”. gem5 implements a simple version of DES compared to, say, SystemC. It is explained in the learning gem5 tutorial. To put it simply : events are scheduled at specific dates. The simulation kernel advances time to the next scheduled event and triggers it. As a result, the callback associated with the event (aka, the process) is executed. These callbacks are implemented by the user to model the system. Processes can schedule events while the are executed, causing the simulation to continue. When a process is over (the callback returns), the sequence I’ve described repeats.

On top of that, gem5 implements a transaction-level-modeling style. This is the generic terminology borrowed from SystemC/TLM and associated with the functional/atomic/timing protocols used in the classic gem5 memory system. Again, this is very well documented but gem5 implements a rather simple version of that approach and thus the learning gem5 resource is the best to understand it.

Regards,

Gabriel.