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Dirty blocks in L1I cache

TP
Theodoros Papavasiliou
Tue, Apr 23, 2024 7:51 AM

Hello everyone,

I'm running some spec2017 benchmarks on gem5 and I noticed there are some
dirty blocks inside the L1 instruction cache. These blocks are also shared
with the L1 data cache.

So, what is a possible explanation for:

  1. having dirty blocks in instruction cache and
  2. having the same blocks in both L1 data and instruction caches?

System configuration
CPU: O3, clock=3.4GHz
L1D: size=32KiB, assoc=8, latency=2
L1I: size=32KiB, assoc=8, latency=2
L2: size=128KiB, assoc=8, latency=15
No prefetchers

Run for 20 million instructions
I'm using private_l1_private_l2_cache_hierarchy.py

Thank you,
Theodoros Papavasileiou

Hello everyone, I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache. These blocks are also shared with the L1 data cache. So, what is a possible explanation for: 1) having dirty blocks in instruction cache and 2) having the same blocks in both L1 data and instruction caches? System configuration CPU: O3, clock=3.4GHz L1D: size=32KiB, assoc=8, latency=2 L1I: size=32KiB, assoc=8, latency=2 L2: size=128KiB, assoc=8, latency=15 No prefetchers Run for 20 million instructions I'm using private_l1_private_l2_cache_hierarchy.py Thank you, Theodoros Papavasileiou
EM
Eliot Moss
Tue, Apr 23, 2024 1:03 PM

On 4/23/2024 3:51 AM, Theodoros Papavasiliou via gem5-users wrote:

Hello everyone,

I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache.
These blocks are also shared with the L1 data cache.

So, what is a possible explanation for:

  1. having dirty blocks in instruction cache and
  2. having the same blocks in both L1 data and instruction caches?

System configuration
CPU: O3, clock=3.4GHz
L1D: size=32KiB, assoc=8, latency=2
L1I: size=32KiB, assoc=8, latency=2
L2: size=128KiB, assoc=8, latency=15
No prefetchers

Run for 20 million instructions
I'm using private_l1_private_l2_cache_hierarchy.py

If the program creates or modifies code, then the created / modified
code will be dirty in the L1 data cache.  If that code is then executed,
it will be fetched into the L1 instruction cache.  It is still dirty in
that it has not yet been written back to main memory.  That's one scenario,
though others may be possible.

Regards - Eliot Moss

On 4/23/2024 3:51 AM, Theodoros Papavasiliou via gem5-users wrote: > Hello everyone, > > I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache. > These blocks are also shared with the L1 data cache. > > So, what is a possible explanation for: > 1) having dirty blocks in instruction cache and > 2) having the same blocks in both L1 data and instruction caches? > > System configuration > CPU: O3, clock=3.4GHz > L1D: size=32KiB, assoc=8, latency=2 > L1I: size=32KiB, assoc=8, latency=2 > L2: size=128KiB, assoc=8, latency=15 > No prefetchers > > Run for 20 million instructions > I'm using private_l1_private_l2_cache_hierarchy.py If the program creates or modifies code, then the created / modified code will be dirty in the L1 data cache. If that code is then executed, it will be fetched into the L1 instruction cache. It is still dirty in that it has not yet been written back to main memory. That's one scenario, though others may be possible. Regards - Eliot Moss
TG
Tianfang Guo
Tue, Apr 23, 2024 1:15 PM

Hi Theodoros,

Unrelated to your question, but if you wouldn't mind sharing, how did you
change the associativity of the private_l1_private_l2_cache_hierarchy.py
from the default 16 to 8?

On Tue, Apr 23, 2024, 4:10 AM Theodoros Papavasiliou via gem5-users <
gem5-users@gem5.org> wrote:

Hello everyone,

I'm running some spec2017 benchmarks on gem5 and I noticed there are some
dirty blocks inside the L1 instruction cache. These blocks are also shared
with the L1 data cache.

So, what is a possible explanation for:

  1. having dirty blocks in instruction cache and
  2. having the same blocks in both L1 data and instruction caches?

System configuration
CPU: O3, clock=3.4GHz
L1D: size=32KiB, assoc=8, latency=2
L1I: size=32KiB, assoc=8, latency=2
L2: size=128KiB, assoc=8, latency=15
No prefetchers

Run for 20 million instructions
I'm using private_l1_private_l2_cache_hierarchy.py

Thank you,
Theodoros Papavasileiou

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Tianfang Guo

Hi Theodoros, Unrelated to your question, but if you wouldn't mind sharing, how did you change the associativity of the private_l1_private_l2_cache_hierarchy.py from the default 16 to 8? On Tue, Apr 23, 2024, 4:10 AM Theodoros Papavasiliou via gem5-users < gem5-users@gem5.org> wrote: > Hello everyone, > > I'm running some spec2017 benchmarks on gem5 and I noticed there are some > dirty blocks inside the L1 instruction cache. These blocks are also shared > with the L1 data cache. > > So, what is a possible explanation for: > 1) having dirty blocks in instruction cache and > 2) having the same blocks in both L1 data and instruction caches? > > System configuration > CPU: O3, clock=3.4GHz > L1D: size=32KiB, assoc=8, latency=2 > L1I: size=32KiB, assoc=8, latency=2 > L2: size=128KiB, assoc=8, latency=15 > No prefetchers > > Run for 20 million instructions > I'm using private_l1_private_l2_cache_hierarchy.py > > Thank you, > Theodoros Papavasileiou > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-leave@gem5.org > Tianfang Guo
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