// simple hit transitions
transition(V, Fetch) {TagArrayRead, DataArrayRead} {

transition(V, StoreThrough, I) {TagArrayRead, TagArrayWrite,  

transition(V, TCC_Ack, V) {TagArrayRead, DataArrayRead, DataArrayWrite} {
  w_writeCache;

Matt Sinclair has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/60652 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-ruby, gpu-compute: update TCP,SQC to pass hit/miss ...................................................................... mem-ruby, gpu-compute: update TCP,SQC to pass hit/miss Previously, the GPU SQC and TCP Ruby protocols always told the Sequencer that the externalHit field was false. This impacts the statistics and profiling, because the Sequencer uses this hit/miss information both for profiling and the coalescer's statistics. To resolve this, this commit updates the GPU SQC and TCP Ruby protocols to pass the appropriate hit/miss information into the Sequencer's readCallback and hitCallback functions. Change-Id: Ib74af09b66fa8866eee72d3a9ab0e8a8f2196c03 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60652 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Matthew Poremba <matthew.poremba@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> --- M src/mem/ruby/protocol/GPU_VIPER-SQC.sm M src/mem/ruby/protocol/GPU_VIPER-TCP.sm 2 files changed, 58 insertions(+), 10 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/protocol/GPU_VIPER-SQC.sm b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm index e0140c9..28bddf5 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-SQC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm @@ -277,7 +277,13 @@ responseToSQC_in.dequeue(clockEdge()); } - action(l_loadDone, "l", desc="local load done") { + action(l_loadDoneHit, "ldh", desc="local load done (hits in SQC)") { + assert(is_valid(cache_entry)); + sequencer.readCallback(address, cache_entry.DataBlk, true, MachineType:L1Cache); + APPEND_TRANSITION_COMMENT(cache_entry.DataBlk); + } + + action(l_loadDoneMiss, "ldm", desc="local load done (misses in SQC)") { assert(is_valid(cache_entry)); sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache); APPEND_TRANSITION_COMMENT(cache_entry.DataBlk); @@ -313,7 +319,7 @@ // don't profile this as a hit/miss since it's a reponse from L2, // so we already counted it w_writeCache; - l_loadDone; + l_loadDoneMiss; pr_popResponseQueue; } @@ -325,7 +331,7 @@ // simple hit transitions transition(V, Fetch) {TagArrayRead, DataArrayRead} { - l_loadDone; + l_loadDoneHit; uu_profileDataHit; // line was in SQC, so we hit p_popMandatoryQueue; } diff --git a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm index 2e8378b..775a62b 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-TCP.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-TCP.sm @@ -453,7 +453,16 @@ responseToTCP_in.dequeue(clockEdge()); } - action(l_loadDone, "l", desc="local load done") { + action(l_loadDoneHit, "ldh", desc="local load done (hits in TCP)") { + assert(is_valid(cache_entry)); + if (use_seq_not_coal) { + sequencer.readCallback(address, cache_entry.DataBlk, true, MachineType:L1Cache); + } else { + coalescer.readCallback(address, MachineType:L1Cache, cache_entry.DataBlk); + } + } + + action(l_loadDoneMiss, "ldm", desc="local load done (misses in TCP)") { assert(is_valid(cache_entry)); if (use_seq_not_coal) { sequencer.readCallback(address, cache_entry.DataBlk, false, MachineType:L1Cache); @@ -467,7 +476,18 @@ coalescer.atomicCallback(address, MachineType:L1Cache, cache_entry.DataBlk); } - action(s_storeDone, "s", desc="local store done") { + action(s_storeDoneHit, "sdh", desc="local store done (hits in TCP)") { + assert(is_valid(cache_entry)); + + if (use_seq_not_coal) { + sequencer.writeCallback(address, cache_entry.DataBlk, true, MachineType:L1Cache); + } else { + coalescer.writeCallback(address, MachineType:L1Cache, cache_entry.DataBlk); + } + cache_entry.Dirty := true; + } + + action(s_storeDoneMiss, "sdm", desc="local store done (misses in TCP)") { assert(is_valid(cache_entry)); if (use_seq_not_coal) { @@ -557,7 +577,7 @@ } transition(V, Load) {TagArrayRead, DataArrayRead} { - l_loadDone; + l_loadDoneHit; mru_updateMRU; uu_profileDataHit; p_popMandatoryQueue; @@ -573,7 +593,7 @@ transition(I, StoreThrough) {TagArrayRead, TagArrayWrite, DataArrayWrite} { a_allocate; dw_dirtyWrite; - s_storeDone; + s_storeDoneMiss; uu_profileDataMiss; wt_writeThrough; ic_invCache; @@ -582,7 +602,7 @@ transition(V, StoreThrough, I) {TagArrayRead, TagArrayWrite, DataArrayWrite} { dw_dirtyWrite; - s_storeDone; + s_storeDoneHit; uu_profileDataHit; wt_writeThrough; ic_invCache; @@ -592,7 +612,7 @@ transition(I, TCC_Ack, V) {TagArrayRead, TagArrayWrite, DataArrayRead, DataArrayWrite} { a_allocate; w_writeCache; - l_loadDone; + l_loadDoneMiss; pr_popResponseQueue; } @@ -618,7 +638,7 @@ transition(V, TCC_Ack, V) {TagArrayRead, DataArrayRead, DataArrayWrite} { w_writeCache; - l_loadDone; + l_loadDoneHit; pr_popResponseQueue; } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/60652 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib74af09b66fa8866eee72d3a9ab0e8a8f2196c03 Gerrit-Change-Number: 60652 Gerrit-PatchSet: 5 Gerrit-Owner: Matt Sinclair <mattdsinclair@gmail.com> Gerrit-Reviewer: Alexandru Duțu <alexandru.dutu@amd.com> Gerrit-Reviewer: Jason Lowe-Power <jason@lowepower.com> Gerrit-Reviewer: Matt Sinclair <mattdsinclair@gmail.com> Gerrit-Reviewer: Matthew Poremba <matthew.poremba@amd.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-MessageType: merged