Dear gem5 community, I developed and tested several 3D network-on-chips in Garnet using internal links for inter-layer communication. As you know, 3D integration is often touted as a method to reduce power consumption. The rationale is that the millimeter-length intra-layer links become significantly shorter in the vertical dimension. To compare the performance of 3D NoCs with their 2D counterparts, I turned to the DSENT simulator. However, my findings were contrary to what I expected. Here are the key observations: *1. Internal Link Lengths:* DSENT does not differentiate between internal links and sets them all to a uniform 1mm length. This oversimplification might have affected the accuracy of my results. *2. Extra Ports in 3D Integration:* One of the fundamental aspects of 3D integration involves adding two extra ports (Up & Down) to facilitate vertical communication. While this enhances connectivity, it also significantly increases the required buffer space, leading to potential power and area overhead. Now, I find myself questioning the validity of my approach. What mistakes might I have made to obtain these unexpected outcomes? Is there an alternative way to design 3D NoCs in Garnet that mitigates the impact of additional ports on power and area? All the best, Ali Karazmoodeh