Hello, my name is Lee Ik-hee and I am researching computer architecture.\ Using the gem5 simulator, I am writing a configuration script to divide the memory address using a heterogeneous memory controller to access dram from 0MB to 512MB and nvm from 512MB to 1024MB, but the nvm side is not accessible from the heterogeneous memory controller. How to solve this problem?\ This is my configuration script. import m5 from m5.objects import \* \ system = System()\ system.clk_domain = SrcClockDomain()system.clk_domain.clock = "1GHz"system.clk_domain.voltage_domain = VoltageDomain()\ system.mem_mode = "timing"system.mem_ranges = \[AddrRange("0MB","512MB"),AddrRange("512MB","1024MB")\]system.cpu = ArmTimingSimpleCPU()\ system.membus = SystemXBar()\ system.cpu.icache_port = system.membus.cpu_side_portssystem.cpu.dcache_port = system.membus.cpu_side_ports\ system.cpu.createInterruptController()\ system.mem_ctrl = HeteroMemCtrl()\ system.mem_ctrl.dram = DDR3_1600_8x8()system.mem_ctrl.dram.range = system.mem_ranges\[0\]\ system.mem_ctrl.nvm = NVM_2400_1x64()system.mem_ctrl.nvm.range = system.mem_ranges\[1\]\ system.mem_ctrl.port = system.membus.mem_side_ports\ system.system_port = system.membus.cpu_side_ports\ thispath = os.path.dirname(os.path.realpath(__file__))binary = os.path.join( thispath, "../../../", "tests/test-progs/hello/bin/arm/linux/hello",)\ system.workload = SEWorkload.init_compatible(binary)\ process = Process()process.cmd = \[binary\]\ system.cpu.workload = processsystem.cpu.createThreads()\ root = Root(full_system=False, system=system)m5.instantiate()\ print(f"Beginning simulation!")exit_event = m5.simulate()print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}") \ Thanks for reading.\ Posted by Lee Ik-hee