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[S] Change in gem5/gem5[develop]: arch-vega: explain when op encoder ignores src reg

MS
Matt Sinclair (Gerrit)
Wed, Jun 22, 2022 5:14 PM

Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/60650 )

Change subject: arch-vega: explain when op encoder ignores src reg
......................................................................

arch-vega: explain when op encoder ignores src reg

Previously b40b361bee8 added support for the Vega operand encoder.  As
part of this, it made sure to check for the S_GETPC_B64 instruction,
which appears to be the only instruction in the Vega ISA that does not
use the source register.  However, at the time the commit used magic
numbers without comment, which can be difficult for users to interpret.

To resolve this, this commit adds a comment to explain where the magic
numbers come from (Table 58 in the Vega ISA manual).

Change-Id: Ic5007b510e0175558d21ede8eb6db273113187b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60650
Maintainer: Matt Sinclair mattdsinclair@gmail.com
Tested-by: kokoro noreply+kokoro@google.com
Reviewed-by: Matthew Poremba matthew.poremba@amd.com
Maintainer: Matthew Poremba matthew.poremba@amd.com

M src/arch/amdgpu/vega/insts/op_encodings.cc
1 file changed, 27 insertions(+), 0 deletions(-)

Approvals:
Matthew Poremba: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, approved
kokoro: Regressions pass

diff --git a/src/arch/amdgpu/vega/insts/op_encodings.cc
b/src/arch/amdgpu/vega/insts/op_encodings.cc
index 4abea2e..45e2e2e 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.cc
+++ b/src/arch/amdgpu/vega/insts/op_encodings.cc
@@ -248,6 +248,10 @@

      // Needed because can't take addr of bitfield
      int reg = instData.SSRC0;
  •    /*
    
  •      S_GETPC_B64 does not use SSRC0, so don't put anything on srcOps
    
  •      for it (0x1c is 29 base 10, which is the opcode for S_GETPC_B64).
    
  •     */
        if (instData.OP != 0x1C) {
            srcOps.emplace_back(reg, getOperandSize(opNum), true,
                                  isScalarReg(instData.SSRC0), false,  
    

false);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5007b510e0175558d21ede8eb6db273113187b2
Gerrit-Change-Number: 60650
Gerrit-PatchSet: 3
Gerrit-Owner: Matt Sinclair mattdsinclair@gmail.com
Gerrit-Reviewer: Alexandru Duțu alexandru.dutu@amd.com
Gerrit-Reviewer: Kyle Roarty kyleroarty1716@gmail.com
Gerrit-Reviewer: Matt Sinclair mattdsinclair@gmail.com
Gerrit-Reviewer: Matthew Poremba matthew.poremba@amd.com
Gerrit-Reviewer: kokoro noreply+kokoro@google.com
Gerrit-MessageType: merged

Matt Sinclair has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/60650 ) Change subject: arch-vega: explain when op encoder ignores src reg ...................................................................... arch-vega: explain when op encoder ignores src reg Previously b40b361bee8 added support for the Vega operand encoder. As part of this, it made sure to check for the S_GETPC_B64 instruction, which appears to be the only instruction in the Vega ISA that does not use the source register. However, at the time the commit used magic numbers without comment, which can be difficult for users to interpret. To resolve this, this commit adds a comment to explain where the magic numbers come from (Table 58 in the Vega ISA manual). Change-Id: Ic5007b510e0175558d21ede8eb6db273113187b2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60650 Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Matthew Poremba <matthew.poremba@amd.com> --- M src/arch/amdgpu/vega/insts/op_encodings.cc 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved; Looks good to me, approved Matt Sinclair: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/amdgpu/vega/insts/op_encodings.cc b/src/arch/amdgpu/vega/insts/op_encodings.cc index 4abea2e..45e2e2e 100644 --- a/src/arch/amdgpu/vega/insts/op_encodings.cc +++ b/src/arch/amdgpu/vega/insts/op_encodings.cc @@ -248,6 +248,10 @@ // Needed because can't take addr of bitfield int reg = instData.SSRC0; + /* + S_GETPC_B64 does not use SSRC0, so don't put anything on srcOps + for it (0x1c is 29 base 10, which is the opcode for S_GETPC_B64). + */ if (instData.OP != 0x1C) { srcOps.emplace_back(reg, getOperandSize(opNum), true, isScalarReg(instData.SSRC0), false, false); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/60650 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic5007b510e0175558d21ede8eb6db273113187b2 Gerrit-Change-Number: 60650 Gerrit-PatchSet: 3 Gerrit-Owner: Matt Sinclair <mattdsinclair@gmail.com> Gerrit-Reviewer: Alexandru Duțu <alexandru.dutu@amd.com> Gerrit-Reviewer: Kyle Roarty <kyleroarty1716@gmail.com> Gerrit-Reviewer: Matt Sinclair <mattdsinclair@gmail.com> Gerrit-Reviewer: Matthew Poremba <matthew.poremba@amd.com> Gerrit-Reviewer: kokoro <noreply+kokoro@google.com> Gerrit-MessageType: merged